PIC18F66K22-I Datasheet, PDF (220/550 Pages) Microchip Technology – PIC18F87K22 Family Data Sheet

PIC18F87K22 FAMILY
FIGURE 16-5:
TIMER3/5/7 GATE SINGLE PULSE AND TOGGLE COMBINED MODE
TMRxGE
TxGPOL
TxGSPM
TxGTM
TxGGO/
TxDONE
TxG_IN
Set by Software
Counting Enabled on
Rising Edge of TxG
Cleared by Hardware on
Falling Edge of TxGVAL
TxCKI
TxGVAL
Timer3/5/7
TMRxGIF
N
Cleared by Software
N+1
N+2
N+3
Set by Hardware on
Falling Edge of TxGVAL
N+4
Cleared by
Software
16.5.5 TIMER3/5/7 GATE VALUE STATUS
When Timer3/5/7 gate value status is utilized, it is
possible to read the most current level of the gate con-
trol value. The value is stored in the TxGVAL bit
(TxGCON<2>). The TxGVAL bit is valid even when the
Timer3/5/7 gate is not enabled (TMRxGE bit is
cleared).
16.5.6
TIMER3/5/7 GATE EVENT
INTERRUPT
When the Timer3/5/7 gate event interrupt is enabled, it
is possible to generate an interrupt upon the comple-
tion of a gate event. When the falling edge of TxGVAL
occurs, the TMRxGIF flag bit in the PIRx register will be
set. If the TMRxGIE bit in the PIEx register is set, then
an interrupt will be recognized.
The TMRxGIF flag bit operates even when the
Timer3/5/7 gate is not enabled (TMRxGE bit is
cleared).
DS39960D-page 220
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