PIC16F627A_05 Datasheet, PDF (45/180 Pages) Microchip Technology – Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology

PIC16F627A/628A/648A
TABLE 5-3: PORTB FUNCTIONS
Name
Function Input Type
Output
Type
Description
RB0/INT
RB0
TTL
CMOS Bidirectional I/O port. Can be software programmed for
internal weak pull-up.
RB1/RX/DT
RB2/TX/CK
RB3/CCP1
RB4/PGM
INT
RB1
RX
DT
RB2
TX
CK
RB3
CCP1
RB4
PGM
RB5
RB5
RB6/T1OSO/T1CKI/
PGC
RB7/T1OSI/PGD
RB6
T1OSO
T1CKI
PGC
RB7
T1OSI
PGD
Legend: O = Output
— = Not used
TTL = TTL Input
ST
—
External interrupt
TTL
CMOS Bidirectional I/O port. Can be software programmed for
internal weak pull-up.
ST
—
USART Receive Pin
ST
CMOS Synchronous data I/O
TTL
CMOS Bidirectional I/O port
—
CMOS USART Transmit Pin
ST
CMOS Synchronous Clock I/O. Can be software programmed
for internal weak pull-up.
TTL
CMOS Bidirectional I/O port. Can be software programmed for
internal weak pull-up.
ST
CMOS Capture/Compare/PWM/I/O
TTL
CMOS Bidirectional I/O port. Interrupt-on-pin change. Can be
software programmed for internal weak pull-up.
ST
—
Low-voltage programming input pin. When low-voltage
programming is enabled, the interrupt-on-pin change
and weak pull-up resistor are disabled.
TTL
CMOS Bidirectional I/O port. Interrupt-on-pin change. Can be
software programmed for internal weak pull-up.
TTL
CMOS Bidirectional I/O port. Interrupt-on-pin change. Can be
software programmed for internal weak pull-up.
—
XTAL Timer1 Oscillator Output
ST
—
Timer1 Clock Input
ST
—
ICSP^™ Programming Clock
TTL
CMOS Bidirectional I/O port. Interrupt-on-pin change. Can be
software programmed for internal weak pull-up.
XTAL
—
Timer1 Oscillator Input
ST
CMOS ICSP Data I/O
CMOS = CMOS Output
I
= Input
OD = Open Drain Output
P = Power
ST = Schmitt Trigger Input
AN = Analog
TABLE 5-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Address Name Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on
All Other
Resets
06h, 106h PORTB RB7
RB6
RB5 RB4⁽¹⁾ RB3
RB2
RB1
RB0 xxxx xxxx uuuu uuuu
86h, 186h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
81h, 181h OPTION RBPU INTEDG T0CS T0SE PSA
PS2
PS1
PS0 1111 1111 1111 1111
Legend: u = unchanged, x = unknown. Shaded cells are not used for PORTB.
Note 1: LVP configuration bit sets RB4 functionality.
© 2005 Microchip Technology Inc.
DS40044D-page 43