PIC16F627A_05 Datasheet, PDF (20/180 Pages) Microchip Technology – Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology

PIC16F627A/628A/648A
4.2.2 SPECIAL FUNCTION REGISTERS
The SFRs are registers used by the CPU and Periph-
eral functions for controlling the desired operation of
the device (Table 4-3). These registers are static RAM.
The special registers can be classified into two sets
(core and peripheral). The SFRs associated with the
“core” functions are described in this section. Those
related to the operation of the peripheral features are
described in the section of that peripheral feature.
TABLE 4-3: SPECIAL REGISTERS SUMMARY BANK0
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Reset⁽¹⁾
Details
on Page
Bank 0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
Legend:
Note 1:
INDF
TMR0
PCL
Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 28
Timer0 Module’s Register
xxxx xxxx 45
Program Counter’s (PC) Least Significant Byte
0000 0000 28
STATUS
FSR
PORTA
PORTB
—
IRP
RP1
RP0
TO
Indirect Data Memory Address Pointer
RA7
RA6
RA5
RA4
RB7
RB6
RB5
RB4
Unimplemented
PD
Z
DC
RA3
RA2
RA1
RB3
RB2
RB1
C
0001 1xxx 22
xxxx xxxx 28
RA0 xxxx 0000 31
RB0 xxxx xxxx 36
—
—
—
Unimplemented
—
Unimplemented
—
—
—
—
PCLATH
—
—
—
Write Buffer for upper 5 bits of Program Counter
---0 0000 28
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF 0000 000x 24
PIR1
EEIF
CMIF
RCIF
TXIF
—
CCP1IF TMR2IF TMR1IF 0000 -000 26
—
Unimplemented
—
—
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx 48
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx 48
T1CON
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 48
TMR2
TMR2 Module’s Register
0000 0000 52
T2CON
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 52
—
Unimplemented
—
—
—
Unimplemented
—
—
CCPR1L Capture/Compare/PWM Register (LSB)
xxxx xxxx 55
CCPR1H Capture/Compare/PWM Register (MSB)
xxxx xxxx 55
CCP1CON —
—
CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 55
RCSTA
SPEN
RX9
SREN
CREN
ADEN
FERR
OERR
RX9D 0000 000x 72
TXREG
USART Transmit Data Register
0000 0000 77
RCREG USART Receive Data Register
0000 0000 80
—
Unimplemented
—
—
—
Unimplemented
—
—
—
Unimplemented
—
Unimplemented
—
—
—
—
CMCON C2OUT C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0 0000 0000 61
- = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
For the initialization condition for registers tables, refer to Table 14-6 and Table 14-7.
DS40044D-page 18
© 2005 Microchip Technology Inc.