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| PIC16F631_08 Datasheet, PDF (41/306 Pages) Microchip Technology – 20-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology | |||
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PIC16F631/677/685/687/689/690
2.2.2.4 PIE1 Register
The PIE1 register contains the interrupt enable bits, as
shown in Register 2-4.
Note: Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
REGISTER 2-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
U-0
â
bit 7
R/W-0
ADIE(5)
R/W-0
RCIE(3)
R/W-0
TXIE(3)
R/W-0
SSPIE(4)
R/W-0
CCP1IE(2)
R/W-0
TMR2IE(1)
R/W-0
TMR1IE
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
â1â = Bit is set
U = Unimplemented bit, read as â0â
â0â = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
3:
4:
5:
Unimplemented: Read as â0â
ADIE: A/D Converter (ADC) Interrupt Enable bit(5)
1 = Enables the ADC interrupt
0 = Disables the ADC interrupt
RCIE: EUSART Receive Interrupt Enable bit(3)
1 = Enables the EUSART receive interrupt
0 = Disables the EUSART receive interrupt
TXIE: EUSART Transmit Interrupt Enable bit(5)
1 = Enables the EUSART transmit interrupt
0 = Disables the EUSART transmit interrupt
SSPIE: Synchronous Serial Port (SSP) Interrupt Enable bit(4)
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
CCP1IE: CCP1 Interrupt Enable bit(2)
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
TMR2IE: Timer2 to PR2 Match Interrupt Enable bit(1)
1 = Enables the Timer2 to PR2 match interrupt
0 = Disables the Timer2 to PR2 match interrupt
TMR1IE: Timer1 Overflow Interrupt Enable bit
1 = Enables the Timer1 overflow interrupt
0 = Disables the Timer1 overflow interrupt
PIC16F685/PIC16F690 only.
PIC16F685/PIC16F689/PIC16F690 only.
PIC16F687/PIC16F689/PIC16F690 only.
PIC16F677/PIC16F687/PIC16F689/PIC16F690 only.
PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only.
© 2008 Microchip Technology Inc.
DS41262E-page 39
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