PIC16F631_08 Datasheet, PDF (205/306 Pages) Microchip Technology – 20-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology

PIC16F631/677/685/687/689/690
14.2.5 TIME-OUT SEQUENCE
On power-up, the time-out sequence is as follows: first,
PWRT time-out is invoked after POR has expired, then
OST is activated after the PWRT time-out has expired.
The total time-out will vary based on oscillator
configuration and PWRTE bit status. For example, in
EC mode with PWRTE bit erased (PWRT disabled),
there will be no time-out at all. Figures 14-4, 14-5
and 14-6 depict time-out sequences. The device can
execute code from the INTOSC while OST is active by
enabling Two-Speed Start-up or Fail-Safe Monitor (see
Section 3.7.2 “Two-speed Start-up Sequence” and
Section 3.8 “Fail-Safe Clock Monitor”).
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then,
bringing MCLR high will begin execution immediately
(see Figure 14-5). This is useful for testing purposes or
to synchronize more than one PIC16F631/677/685/
687/689/690 device operating in parallel.
Table 14-5 shows the Reset conditions for some
special registers, while Table 14-4 shows the Reset
conditions for all the registers.
14.2.6 POWER CONTROL (PCON)
REGISTER
The Power Control register PCON (address 8Eh) has
two Status bits to indicate what type of Reset that last
occurred.
Bit 0 is BOR (Brown-out Reset). BOR is unknown on
Power-on Reset. It must then be set by the user and
checked on subsequent Resets to see if BOR = 0,
indicating that a Brown-out has occurred. The BOR
Status bit is a “don’t care” and is not necessarily
predictable if the brown-out circuit is disabled
(BOREN<1:0> = 00 in the Configuration Word
register).
Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on
Reset and unaffected otherwise. The user must write a
‘1’ to this bit following a Power-on Reset. On a
subsequent Reset, if POR is ‘0’, it will indicate that a
Power-on Reset has occurred (i.e., VDD may have
gone too low).
For more information, see Section 4.2.4 “Ultra Low-
Power Wake-up” and Section 14.2.4 “Brown-out
Reset (BOR)”.
TABLE 14-1: TIME-OUT IN VARIOUS SITUATIONS
Oscillator Configuration
Power-up
PWRTE = 0
PWRTE = 1
XT, HS, LP
LP, T1OSCIN = 1
RC, EC, INTOSC
TPWRT +
1024 • TOSC
TPWRT
TPWRT
1024 • TOSC
—
—
Brown-out Reset
PWRTE = 0
TPWRT +
1024 • TOSC
TPWRT
TPWRT
PWRTE = 1
1024 • TOSC
—
—
Wake-up from
Sleep
1024 • TOSC
—
—
TABLE 14-2: STATUS/PCON BITS AND THEIR SIGNIFICANCE
POR
BOR
TO
PD
Condition
0
x
1
1
u
0
1
1
u
u
0
u
u
u
0
0
u
u
u
u
u
u
1
0
Legend: u = unchanged, x = unknown
Power-on Reset
Brown-out Reset
WDT Reset
WDT Wake-up
MCLR Reset during normal operation
MCLR Reset during Sleep
TABLE 14-3: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
PCON
STATUS
Legend:
Note 1:
—
—
ULPWUE SBOREN
—
—
POR
BOR
--01 --qq --0u --uu
IRP
RP1
RPO
TO
PD
Z
DC
C
0001 1xxx 000q quuu
u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition. Shaded cells are not used by BOR.
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
© 2008 Microchip Technology Inc.
DS41262E-page 203