PIC16F631_08 Datasheet, PDF (105/306 Pages) Microchip Technology – 20-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology

PIC16F631/677/685/687/689/690
REGISTER 8-4: SRCON: SR LATCH CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/S-0
R/S-0
U-0
SR1⁽²⁾
SR0⁽²⁾
C1SEN
C2REN
PULSS
PULSR
—
bit 7
U-0
—
bit 0
Legend:
R = Readable bit
-n = Value at POR
S = Bit is set only
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
SR1: SR Latch Configuration bit⁽²⁾
1 = C2OUT pin is the latch Q output
0 = C2OUT pin is the C2 comparator output
SR0: SR Latch Configuration bits⁽²⁾
1 = C1OUT pin is the latch Q output
0 = C1OUT pin is the Comparator C1 output
C1SEN: C1 Set Enable bit
1 = C1 comparator output sets SR latch
0 = C1 comparator output has no effect on SR latch
C2REN: C2 Reset Enable bit
1 = C2 comparator output resets SR latch
0 = C2 comparator output has no effect on SR latch
PULSS: Pulse the SET Input of the SR Latch bit
1 = Triggers pulse generator to set SR latch. Bit is immediately reset by hardware.
0 = Does not trigger pulse generator
PULSR: Pulse the Reset Input of the SR Latch bit
1 = Triggers pulse generator to reset SR latch. Bit is immediately reset by hardware.
0 = Does not trigger pulse generator
Unimplemented: Read as ‘0’
Note 1: The CxOUT bit in the CMxCON0 register will always reflect the actual comparator output (not the level on
the pin), regardless of the SR latch operation.
2: To enable an SR latch output to the pin, the appropriate CxOE and TRIS bits must be properly configured.
© 2008 Microchip Technology Inc.
DS41262E-page 103