PIC16F631_08 Datasheet, PDF (254/306 Pages) Microchip Technology – 20-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology

PIC16F631/677/685/687/689/690
TABLE 17-12: SPI MODE REQUIREMENTS
Param
No.
Symbol
Characteristic
Min. Typ† Max. Units Conditions
70* TSSL2SCH, SS↓ to SCK↓ or SCK↑ input
TSSL2SCL
TCY
— — ns
71* TSCH
SCK input high time (Slave mode)
TCY + 20 — — ns
72* TSCL
SCK input low time (Slave mode)
TCY + 20 — — ns
73* TDIV2SCH, Setup time of SDI data input to SCK edge
TDIV2SCL
100
— — ns
74* TSCH2DIL, Hold time of SDI data input to SCK edge
TSCL2DIL
100
— — ns
75* TDOR
SDO data output rise time
3.0-5.5V
—
10 25 ns
2.0-5.5V
—
25 50 ns
76* TDOF
SDO data output fall time
—
10 25 ns
77* TSSH2DOZ SS↑ to SDO output high-impedance
10
— 50 ns
78* TSCR
SCK output rise time
(Master mode)
3.0-5.5V
2.0-5.5V
—
10 25 ns
—
25 50 ns
79* TSCF
SCK output fall time (Master mode)
—
10 25 ns
80* TSCH2DOV, SDO data output valid after
TSCL2DOV SCK edge
3.0-5.5V
2.0-5.5V
—
— 50 ns
—
— 145 ns
81* TDOV2SCH, SDO data output setup to SCK edge
TDOV2SCL
Tcy
— — ns
82* TSSL2DOV SDO data output valid after SS↓ edge
—
— 50 ns
83* TSCH2SSH, SS ↑ after SCK edge
TSCL2SSH
1.5TCY + 40 — — ns
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
FIGURE 17-16: I²C™ BUS START/STOP BITS TIMING
SCL
SDA
91
90
93
92
Start
Condition
Note: Refer to Figure 17-3 for load conditions.
Stop
Condition
DS41262E-page 252
© 2008 Microchip Technology Inc.