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| PIC16F631_08 Datasheet, PDF (211/306 Pages) Microchip Technology – 20-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology | |||
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PIC16F631/677/685/687/689/690
14.3.2 TIMER0 INTERRUPT
An overflow (FFh â 00h) in the TMR0 register will set
the T0IF (INTCON<2>) bit. The interrupt can be
enabled/disabled by setting/clearing T0IE (INTCON<5>)
bit. See Section 5.0 âTimer0 Moduleâ for operation of
the Timer0 module.
FIGURE 14-7:
IOC-RA0
IOCA0
IOC-RA1
IOCA1
IOC-RA2
IOCA2
IOC-RA3
IOCA3
IOC-RA4
IOCA4
IOC-RA5
IOCA5
IOC-RB4
IOCB4
IOC-RB5
IOCB5
IOC-RB6
IOCB6
IOC-RB7
IOCB7
INTERRUPT LOGIC
SSPIF
SSPIE
TXIF
TXIE
RCIF
RCIE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
C1IF
C1IE
C2IF
C2IE
ADIF
ADIE
EEIF
EEIE
OSFIF
OSFIE
CCP1IF
CCP1IE
14.3.3 PORTA/PORTB INTERRUPT
An input change on PORTA or PORTB change sets the
RABIF (INTCON<0>) bit. The interrupt can be enabled/
disabled by setting/clearing the RABIE (INTCON<3>)
bit. Plus, individual pins can be configured through the
IOCA or IOCB registers.
Note:
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RABIF
interrupt flag may not get set. See
Section 4.2.3 âInterrupt-on-changeâ for
more information.
T0IF
T0IE
INTF
INTE
RABIF
RABIE
PEIE
GIE
Wake-up (If in Sleep mode)(1)
Interrupt to CPU
Note 1:
Some peripherals depend upon the system
clock for operation. Since the system clock is
suspended during Sleep, these peripherals
will not wake the part from Sleep. See
Section 14.6.1 âWake-up from Sleepâ.
© 2008 Microchip Technology Inc.
DS41262E-page 209
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