PIC16F631_08 Datasheet, PDF (190/306 Pages) Microchip Technology – 20-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology

PIC16F631/677/685/687/689/690
13.11 SSP I²C Operation
The SSP module in I²C mode, fully implements all slave
functions, except general call support, and provides
interrupts on Start and Stop bits in hardware to facilitate
firmware implementations of the master functions. The
SSP module implements the Standard mode
specifications, as well as 7-bit and 10-bit addressing.
Two pins are used for data transfer. These are the RB6/
SCK/SCL pin, which is the clock (SCL), and the RB4/
AN10/SDI/SDA pin, which is the data (SDA).
The SSP module functions are enabled by setting SSP
enable bit SSPEN (SSPCON<5>).
FIGURE 13-7:
SSP BLOCK DIAGRAM
(I²C™ MODE)
RB6/
SCK/
SCL
RB4/
AN10/
SDI/SDA
Read
Internal
Data Bus
Write
SSPBUF Reg
Shift
Clock
SSPSR Reg
MSb
LSb
Match Detect
Addr Match
SSPMSK Reg
SSPADD Reg
Start and
Stop bit Detect
Set, Reset
S, P bits
(SSPSTAT Reg)
The SSP module has six registers for the I²C operation,
which are listed below.
• SSP Control register (SSPCON)
• SSP Status register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift register (SSPSR) – Not directly
accessible
• SSP Address register (SSPADD)
• SSP Mask register (SSPMSK)
The SSPCON register allows control of the I²C
operation. Four mode selection bits (SSPCON<3:0>)
allow one of the following I²C modes to be selected:
• I²C Slave mode (7-bit address)
• I²C Slave mode (10-bit address)
• I²C Slave mode (7-bit address), with Start and
Stop bit interrupts enabled to support Firmware
Master mode
• I²C Slave mode (10-bit address), with Start and
Stop bit interrupts enabled to support Firmware
Master mode
• I²C Start and Stop bit interrupts enabled to
support Firmware Master mode; Slave is idle
Selection of any I²C mode with the SSPEN bit set
forces the SCL and SDA pins to be open drain,
provided these pins are programmed to inputs by
setting the appropriate TRISB bits. Pull-up resistors
must be provided externally to the SCL and SDA pins
for proper operation of the I²C module.
13.12 Slave Mode
In Slave mode, the SCL and SDA pins must be
configured as inputs (TRISB<6,4> are set). The SSP
module will override the input state with the output data
when required (slave-transmitter).
When an address is matched, or the data transfer after
an address match is received, the hardware
automatically will generate the Acknowledge (ACK)
pulse, and then load the SSPBUF register with the
received value currently in the SSPSR register.
There are certain conditions that will cause the SSP
module not to give this ACK pulse. They include (either
or both):
a) The Buffer Full bit BF of the SSPSTAT register
was set before the transfer was received.
b) The overflow bit SSPOV of the SSPCON
register was set before the transfer was
received.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF of the PIR1 register is
set. Table 13-3 shows the results of when a data
transfer byte is received, given the status of bits BF and
SSPOV. The shaded cells show the condition where
user software did not properly clear the overflow
condition. Flag bit BF is cleared by reading the
SSPBUF register, while bit SSPOV is cleared through
software.
The SCL clock input must have a minimum high and low
for proper operation. For high and low times of the I²C
specification, as well as the requirements of the SSP
module, see Section 17.0 “Electrical Specifications”.
DS41262E-page 188
© 2008 Microchip Technology Inc.