PIC16F1938_13 Datasheet, PDF(33/488 Page) Microchip Technology – 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver

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PIC16F1938_13 Datasheet, PDF (33/488 Pages) Microchip Technology – 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver

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PIC16(L)F1938/9

TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on all

other

Resets

Bank 1

080h(2) INDF0

081h(2) INDF1

082h(2) PCL

083h(2) STATUS

084h(2) FSR0L

085h(2) FSR0H

086h(2) FSR1L

087h(2) FSR1H

088h(2) BSR

089h(2) WREG

08Ah(1, 2) PCLATH

08Bh(2) INTCON

Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register)

Program Counter (PC) Least Significant Byte

â

â

â

TO

PD

Z

DC

Indirect Data Memory Address 0 Low Pointer

Indirect Data Memory Address 0 High Pointer

Indirect Data Memory Address 1 Low Pointer

Indirect Data Memory Address 1 High Pointer

â

â

â

BSR<4:0>

Working Register

â Write Buffer for the upper 7 bits of the Program Counter

GIE

PEIE

TMR0IE

INTE

IOCIE TMR0IF INTF

xxxx xxxx xxxx xxxx

xxxx xxxx xxxx xxxx

C

IOCIF

0000 0000 0000 0000

---1 1000 ---q quuu

0000 0000 uuuu uuuu

0000 0000 0000 0000

0000 0000 uuuu uuuu

0000 0000 0000 0000

---0 0000 ---0 0000

0000 0000 uuuu uuuu

-000 0000 -000 0000

0000 0000 0000 0000

08Ch

TRISA

PORTA Data Direction Register

1111 1111 1111 1111

08Dh

TRISB

PORTB Data Direction Register

1111 1111 1111 1111

08Eh

08Fh(3)

090h

TRISC

TRISD

TRISE

PORTC Data Direction Register

PORTD Data Direction Register

â

â

â

1111 1111 1111 1111

1111 1111 1111 1111

â

â(4)

TRISE2(3) TRISE1(3) TRISE0(3) ---- 1111 ---- 1111

091h

PIE1

TMR1GIE ADIE

RCIE

TXIE

SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

092h

PIE2

OSFIE

C2IE

C1IE

EEIE

BCLIE

LCDIE

â

CCP2IE 0000 00-0 0000 00-0

093h

PIE3

â

CCP5IE CCP4IE CCP3IE TMR6IE

â

TMR4IE

â -000 0-0- -000 0-0-

094h

â

Unimplemented

â

â

095h

OPTION_REG WPUEN INTEDG TMROCS TMROSE

PSA

PS<2:0>

1111 1111 1111 1111

096h

PCON

STKOVF STKUNF

â

â

RMCLR

RI

POR

BOR 00-- 11qq qq-- qquu

097h

WDTCON

â

â

WDTPS<4:0>

SWDTEN --01 0110 --01 0110

098h

OSCTUNE

â

â

TUN<5:0>

--00 0000 --00 0000

099h

OSCCON

SPLLEN

IRCF<3:0>

â

SCS<1:0>

0011 1-00 0011 1-00

09Ah

OSCSTAT

T1OSCR PLLR

OSTS

HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS 00q0 0q0- qqqq qq0-

09Bh

ADRESL

A/D Result Register Low

xxxx xxxx uuuu uuuu

09Ch

ADRESH

A/D Result Register High

xxxx xxxx uuuu uuuu

09Dh

ADCON0

â

CHS<4:0>

GO/DONE ADON -000 0000 -000 0000

09Eh

ADCON1

ADFM

ADCS<2:0>

â

ADNREF ADPREF1 ADPREF0 0000 -000 0000 -000

09Fh

â

Unimplemented

â

â

Legend:

Note 1:

2:

3:

4:

x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as â0â, r = reserved.

Shaded locations are unimplemented, read as â0â.

The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are

transferred to the upper byte of the program counter.

These registers can be addressed from any bank.

These registers/bits are not implemented on PIC16(L)F1938 devices, read as â0â.

Unimplemented, read as â1â.

ï£ 2011-2013 Microchip Technology Inc.

DS40001574C-page 33

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