PIC16F1938_13 Datasheet, PDF (311/488 Pages) Microchip Technology – 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver

PIC16(L)F1938/9
FIGURE 25-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
RX/DT
pin
TX/CK pin
(SCKP = 0)
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TX/CK pin
(SCKP = 1)
Write to
bit SREN
SREN bit
CREN bit ^{‘0’}
‘0’
RCIF bit
(Interrupt)
Read
RXREG
Note:
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TABLE 25-8: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER
RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
BAUDCON ABDOVF RCIDL
—
SCKP BRG16
—
WUE ABDEN
298
INTCON
GIE
PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF
90
PIE1
TMR1GIE ADIE
RCIE
TXIE SSPIE CCP1IE TMR2IE TMR1IE
91
PIR1
TMR1GIF ADIF
RCIF
TXIF SSPIF CCP1IF TMR2IF TMR1IF
94
RCREG
EUSART Receive Data Register
292*
RCSTA
SPEN
RX9
SREN CREN ADDEN FERR OERR RX9D
297
SPBRGL
BRG<7:0>
299*
SPBRGH
BRG<15:8>
299*
TRISC
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
134
TXSTA
CSRC
TX9
TXEN SYNC SENDB BRGH TRMT TX9D
296
Legend: — = unimplemented location read as ‘0’. Shaded cells are not used for synchronous master reception.
* Page provides register information.
 2011-2013 Microchip Technology Inc.
DS40001574C-page 311