PIC16F1938_13 Datasheet, PDF (180/488 Pages) Microchip Technology – 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver

PIC16(L)F1938/9
19.2 Latch Output
The SRQEN and SRNQEN bits of the SRCON0 regis-
ter control the Q and Q latch outputs. Both of the SR
Latch outputs may be directly output to an I/O pin at the
same time. The Q latch output pin function can be
moved to an alternate pin using the SRNQSEL bit of
the APFCON register.
The applicable TRIS bit of the corresponding port must
be cleared to enable the port pin output driver.
19.3 Effects of a Reset
Upon any device Reset, the SR Latch output is not ini-
tialized to a known state. The user’s firmware is
responsible for initializing the latch output before
enabling the output pins.
FIGURE 19-1:
SR LATCH SIMPLIFIED BLOCK DIAGRAM
SRPS
Pulse
Gen⁽²⁾
SRLEN
SRQEN
SRI
SRSPE
SRCLK
SRSCKE
sync_C2OUT⁽³⁾
SRSC2E
sync_C1OUT⁽³⁾
SRSC1E
SRPR
Pulse
Gen⁽²⁾
SQ
SR
Latch⁽¹⁾
SRQ
SRI
SRRPE
SRCLK
SRRCKE
sync_C2OUT⁽³⁾
SRRC2E
sync_C1OUT⁽³⁾
SRRC1E
RQ
SRLEN
SRNQEN
SRNQ
Note 1:
2:
3:
If R = 1 and S = 1 simultaneously, Q = 0, Q = 1
Pulse generator causes a 1 Q-state pulse width.
Name denotes the connection point at the comparator output.
DS40001574C-page 180
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