PIC16F1938_13 Datasheet, PDF (167/488 Pages) Microchip Technology – 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver

PIC16(L)F1938/9
17.4 Low-Power Voltage State
In order for the DAC module to consume the least
amount of power, one of the two voltage reference input
sources to the resistor ladder must be disconnected.
Either the positive voltage source, (VSOURCE+), or the
negative voltage source, (VSOURCE-) can be disabled.
The negative voltage source is disabled by setting the
DACLPS bit in the DACCON0 register. Clearing the
DACLPS bit in the DACCON0 register disables the
positive voltage source.
17.4.1 OUTPUT CLAMPED TO POSITIVE
VOLTAGE SOURCE
The DAC output voltage can be set to VSOURCE+ with
the least amount of power consumption by performing
the following:
• Clearing the DACEN bit in the DACCON0 register.
• Setting the DACLPS bit in the DACCON0 register.
• Configuring the DACPSS bits to the proper
positive source.
• Configuring the DACR<4:0> bits to ‘11111’ in the
DACCON1 register.
This is also the method used to output the voltage level
from the FVR to an output pin. See Section 17.5
“Operation During Sleep” for more information.
Reference Figure 17-3 for output clamping examples.
17.4.2 OUTPUT CLAMPED TO NEGATIVE
VOLTAGE SOURCE
The DAC output voltage can be set to VSOURCE- with
the least amount of power consumption by performing
the following:
• Clearing the DACEN bit in the DACCON0 register.
• Clearing the DACLPS bit in the DACCON0 register.
• Configuring the DACNSS bits to the proper
negative source.
• Configuring the DACR<4:0> bits to ‘00000’ in the
DACCON1 register.
This allows the comparator to detect a zero-crossing
while not consuming additional current through the DAC
module.
Reference Figure 17-3 for output clamping examples.
FIGURE 17-3:
OUTPUT VOLTAGE CLAMPING EXAMPLES
Output Clamped to Positive Voltage Source
Output Clamped to Negative Voltage Source
VSOURCE+
DACEN = 0
DACLPS = 1
VSOURCE-
R
DACR<4:0> = 11111
R
DAC Voltage Ladder
(see Figure 17-1)
R
VSOURCE+
DACEN = 0
DACLPS = 0
VSOURCE-
R
R
DAC Voltage Ladder
(see Figure 17-1)
R _{DACR<4:0> = 00000}
17.5 Operation During Sleep
When the device wakes up from Sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the DACCON0 register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.
17.6 Effects of a Reset
A device Reset affects the following:
• DAC is disabled.
• DAC output voltage is removed from the
DACOUT pin.
• The DACR<4:0> range select bits are cleared.
 2011-2013 Microchip Technology Inc.
DS40001574C-page 167