PIC16F1938_13 Datasheet, PDF (182/488 Pages) Microchip Technology – 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver

PIC16(L)F1938/9
19.4 Register Definitions: SR Latch Control
REGISTER 19-1: SRCON0: SR LATCH CONTROL 0 REGISTER
R/W-0/0
SRLEN
bit 7
R/W-0/0
R/W-0/0
SRCLK<2:0>
R/W-0/0
R/W-0/0
SRQEN
R/W-0/0
SRNQEN
R/S-0/0
SRPS
R/S-0/0
SRPR
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
S = Bit is set only
bit 7
bit 6-4
bit 3
bit 2
bit 1
bit 0
SRLEN: SR Latch Enable bit
1 = SR Latch is enabled
0 = SR Latch is disabled
SRCLK<2:0>: SR Latch Clock Divider bits
111 = Generates a 1 FOSC wide pulse every 512th FOSC cycle clock
110 = Generates a 1 FOSC wide pulse every 256th FOSC cycle clock
101 = Generates a 1 FOSC wide pulse every 128th FOSC cycle clock
100 = Generates a 1 FOSC wide pulse every 64th FOSC cycle clock
011 = Generates a 1 FOSC wide pulse every 32nd FOSC cycle clock
010 = Generates a 1 FOSC wide pulse every 16th FOSC cycle clock
001 = Generates a 1 FOSC wide pulse every 8th FOSC cycle clock
000 = Generates a 1 FOSC wide pulse every 4th FOSC cycle clock
SRQEN: SR Latch Q Output Enable bit
If SRLEN = 1:
1 = Q is present on the SRQ pin
0 = External Q output is disabled
If SRLEN = 0:
SR Latch is disabled
SRNQEN: SR Latch Q Output Enable bit
If SRLEN = 1:
1 = Q is present on the SRnQ pin
0 = External Q output is disabled
If SRLEN = 0:
SR Latch is disabled
SRPS: Pulse Set Input of the SR Latch bit⁽¹⁾
1 = Pulse set input for 1 Q-clock period
0 = No effect on set input.
SRPR: Pulse Reset Input of the SR Latch bit⁽¹⁾
1 = Pulse reset input for 1 Q-clock period
0 = No effect on reset input.
Note 1: Set only, always reads back ‘0’.
DS40001574C-page 182
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