PIC16F1938_13 Datasheet, PDF (245/488 Pages) Microchip Technology – 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver

PIC16(L)F1938/9
24.2.6 SPI OPERATION IN SLEEP MODE
In SPI Master mode, module clocks may be operating
at a different speed than when in Full-Power mode; in
the case of the Sleep mode, all clocks are halted.
Special care must be taken by the user when the MSSP
clock is much faster than the system clock.
In Slave mode, when MSSP interrupts are enabled,
after the master completes sending data, an MSSP
interrupt will wake the controller from Sleep.
If an exit from Sleep mode is not desired, MSSP
interrupts should be disabled.
In SPI Master mode, when the Sleep mode is selected,
all module clocks are halted and the transmis-
sion/reception will remain in that state until the device
wakes. After the device returns to Run mode, the mod-
ule will resume transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in Sleep mode and data
to be shifted into the SPI Transmit/Receive Shift
register. When all eight bits have been received, the
MSSP interrupt flag bit will be set and if enabled, will
wake the device.
TABLE 24-1: SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSELA
—
—
ANSA5 ANSA4
ANSA3
ANSA2
ANSA1
ANSA0
APFCON
—
CCP3SEL T1GSEL P2BSEL SRNQSEL C2OUTSEL SSSEL CCP2SEL
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
PIE1
TMR1GIE ADIE
RCIE
TXIE
SSP1IE
CCP1IE TMR2IE TMR1IE
PIR1
TMR1GIF ADIF
RCIF
TXIF
SSP1IF
CCP1IF TMR2IF TMR1IF
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register
SSPCON1 WCOL
SSPOV
SSPEN
CKP
SSPM<3:0>
SSPCON3 ACKTIM
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN
SSPSTAT
TRISA
SMP
TRISA7
CKE
TRISA6
D/A
TRISA5
P
TRISA4
S
TRISA3
R/W
TRISA2
UA
TRISA1
BF
TRISA0
TRISC
TRISC7 TRISC6 TRISC5 TRISC4
TRISC3
TRISB2 TRISC1 TRISC0
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.
* Page provides register information.
126
123
90
91
94
239*
283
285
282
125
134
 2011-2013 Microchip Technology Inc.
DS40001574C-page 245