PIC16F1933_11 Datasheet, PDF(29/430 Page) Microchip Technology – 28-Pin Flash-Based, 8-Bit CMOS Microcontrollers LCD Driver and nanoWatt XLP Technology

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PIC16F1933_11 Datasheet, PDF (29/430 Pages) Microchip Technology – 28-Pin Flash-Based, 8-Bit CMOS Microcontrollers LCD Driver and nanoWatt XLP Technology

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PIC16(L)F1933

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TABLE 3-9: SPECIAL FUNCTION REGISTER SUMMARY

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on all

other

Resets

Bank 0

000h(2) INDF0

Addressing this location uses contents of FSR0H/FSR0L to Address Data Memory

(not a physical register)

xxxx xxxx xxxx xxxx

001h(2) INDF1

Addressing this location uses contents of FSR1H/FSR1L to Address Data Memory

(not a physical register)

xxxx xxxx xxxx xxxx

002h(2) PCL

Program Counter (PC) Least Significant Byte

0000 0000 0000 0000

003h(2) STATUS

â

â

â

TO

PD

Z

DC

C

---1 1000 ---q quuu

004h(2) FSR0L

Indirect Data Memory Address 0 Low Pointer

0000 0000 uuuu uuuu

005h(2) FSR0H

Indirect Data Memory Address 0 High Pointer

0000 0000 0000 0000

006h(2) FSR1L

Indirect Data Memory Address 1 Low Pointer

0000 0000 uuuu uuuu

007h(2) FSR1H

Indirect Data Memory Address 1 High Pointer

0000 0000 0000 0000

008h(2) BSR

â

â

â

BSR<4:0>

---0 0000 ---0 0000

009h(2) WREG

Working Register

0000 0000 uuuu uuuu

00Ah(1, 2) PCLATH

â

Write Buffer for the upper 7 bits of the Program Counter

-000 0000 -000 0000

00Bh(2) INTCON

GIE

PEIE

TMR0IE

INTE

IOCIE

TMR0IF

INTF

IOCIF 0000 0000 0000 0000

00Ch

PORTA

PORTA Data Latch when written: PORTA pins when read

xxxx xxxx uuuu uuuu

00Dh

PORTB

PORTB Data Latch when written: PORTB pins when read

xxxx xxxx uuuu uuuu

00Eh

PORTC

PORTC Data Latch when written: PORTC pins when read

xxxx xxxx uuuu uuuu

00Fh

â

Unimplemented

â

â

010h

PORTE

â

â

â

â

RE3

â

â

â

---- x--- ---- u---

011h

PIR1

TMR1GIF

ADIF

RCIF

TXIF

SSPIF

CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

012h

PIR2

OSFIF

C2IF

C1IF

EEIF

BCLIF

LCDIF

â

CCP2IF 0000 00-0 0000 00-0

013h

PIR3

â

CCP5IF

CCP4IF

CCP3IF

TMR6IF

â

TMR4IF

â

-000 0-0- -000 0-0-

014h

â

Unimplemented

â

â

015h

TMR0

Timer0 Module Register

xxxx xxxx uuuu uuuu

016h

TMR1L

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

xxxx xxxx uuuu uuuu

017h

TMR1H

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

xxxx xxxx uuuu uuuu

018h

T1CON

TMR1CS<1:0>

T1CKPS<1:0>

T1OSCEN T1SYNC

â

TMR1ON 0000 00-0 uuuu uu-u

019h

T1GCON

TMR1GE T1GPOL

T1GTM

T1GSPM

T1GGO/

DONE

T1GVAL

T1GSS<1:0>

0000 0x00 uuuu uxuu

01Ah

TMR2

Timer 2 Module Register

0000 0000 0000 0000

01Bh

PR2

Timer 2 Period Register

1111 1111 1111 1111

01Ch

T2CON

â

T2OUTPS<3:0>

TMR2ON

T2CKPS<1:0>

-000 0000 -000 0000

01Dh

â

Unimplemented

â

â

01Eh

CPSCON0

CPSON CPSRM

â

â

CPSRNG1 CPSRNG0 CPSOUT T0XCS 00-- 0000 00-- 0000

01Fh

CPSCON1

â

â

â

â

â

CPSCH<2:0>

---- -000 ---- -000

Legend:

Note 1:

2:

3:

x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as â0â, r = reserved.

Shaded locations are unimplemented, read as â0â.

The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred

to the upper byte of the program counter.

These registers can be addressed from any bank.

Unimplemented, read as â1â.

ï£ 2011 Microchip Technology Inc.

Preliminary

DS41575A-page 29

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