MLX71122_16 Datasheet, PDF (7/59 Pages) Melexis Microelectronic Systems – 300 to 930MHz FSK/FM/ASK Receiver

MLX71122
300 to 930MHz FSK/FM/ASK Receiver
Datasheet
1.2. Technical Data Overview
 Input frequency ranges: 300 to 930MHz
 Power supply range: 3.0 to 5.5V
 Temperature range: -40 to +110°C
 Shutdown current: 50nA
 Operating current: 12mA (typ.)
 FSK input sensitivity: -107dBm (typ.)
 ASK input sensitivity: -112dBm (typ.)
 Internal IF2: 2MHz with 230kHz 3dB
bandwidth
 Maximum data rate: 100kbps NRZ code,
50kbps bi-phase code
 Minimum frequency resolution: 10kHz
 Total image rejection: > 65dB (with
external RF front-end filter)
 FSK/FM deviation range: ±10 to ±50kHz
 Spurious emission: < -70dBm
 Linear RSSI range: > 50dB
 FSK input frequency acceptance range:
 180kHz (3dB sensitivity loss)
 Crystal reference frequency: 10MHz
1.3. Block Diagram
123456
LNAI _LNA
31
MIX1
MIX2
IFF
IF1
IF2
LO1
LO2
LO2DIV
VCO
N/A
counter
LF
PFD
R
counter
CP RO
11 14 TNK1 12 13 TNK2 15 23
24
8
IFA
Control
Logic
9
ASK
FSK
SW1
FSK
DEMOD
SLCSEL
BIAS
28
200k
SW2
29
200k
DFO
OA1
27
PKDET+ 25
PDP
PKDET_ PDN
26
OA2
DTAO
22
SLC
32
7 17 18 19
10 16
20 21 30
Fig. 1: MLX71122 block diagram
The MLX71122 receiver IC consists of the following building blocks:
 PLL synthesizer (PLL SYNTH) to generate the first and second local oscillator signals LO1 and LO2, parts
of the PLL SYNTH are the voltage-controlled oscillator (VCO), the feedback dividers N/A and R, the
phase-frequency detector (PFD), the charge pump (CP) and the crystal-based reference oscillator (RO)
 Low-noise amplifier (LNA) for high-sensitivity RF signal reception
 First mixer (MIX1) for down-conversion of the RF signal to the first IF (intermediate frequency)
 Second mixer (MIX2) with image rejection for down-conversion from the first to the second IF
 IF Filter (IFF) with a 2MHz center frequency and a 230kHz 3dB bandwidth
 IF amplifier (IFA) to provide a large amount of voltage gain and an RSSI signal output
 FSK demodulator (FSK DEMOD)
 Operational amplifiers OA1 and OA2 for low-pass filtering and data slicing, respectively
 Positive (PKDET+) and negative (PKDET-) peak detectors
 Switches SW1 to select between FSK and ASK as well as SW2 to chose between averaging or peak
detector data slicer
 Control logic with 3-wire bus serial programming interface (SPI)
 Biasing circuit with modes control
REVISION 014 – AUGUST, 2016
390 10 71122 01
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