MLX71122_16 Datasheet, PDF (27/59 Pages) Melexis Microelectronic Systems – 300 to 930MHz FSK/FM/ASK Receiver

MLX71122
300 to 930MHz FSK/FM/ASK Receiver
Datasheet
Band / MHz
315
434
868
915
L0 inductor / nH
33
22
5.6
5.6
Typical VCO Gain
K_VCO / MHz/V, VCCRANGE=0
128
188
222
250
K_VCO / MHz/V, VCCRANGE=1
60
85
108
116
The phase margin Φ_M determines the stability of the PLL. It should be larger than 45°. A phase margin of
56.4° should be preferred.
The closed loop PLL bandwidth f_C of a receiver should be as large as possible in order to allow fast settling
of the frequency. On the other hand it should be so low that the reference spurs at the PFD frequency are
sufficiently suppressed. A good compromise is to make f_C 1/10 of the PFD frequency. Therefore it is
desirable to make f_PFD as large as possible or the R divider as small as possible but not smaller than 20.
The feedback ratio between the VCO output frequency and the PFD frequency shall be called N.
The following empirically derived formulas are rules of thumb for a phase margin of 56.4° and for
receivers.
ω_U shall be the unity gain bandwidth in rad/s of the open loop PLL transfer function.
_U

2 f_C
1.62
(19)
a₀
 3.3
I _CP  K_VCO
N  _U²
(20)
C_F2

a₀
11
(21)
C_F1

a₀ 10
11
(22)
R_F

3.63
a₀  _U
(23)
The loop filter elements for 868 and 915MHz in the evaluation board list in section 6.3 are scaled values of
the calculated values in order to reduce the capacitance value. If the capacitors are scaled down then the
resistor needs to be scaled up by the same factor and vice versa.
REVISION 014 – AUGUST, 2016
390 10 71122 01
Page 27 of 59