MLX71122_16 Datasheet, PDF (44/59 Pages) Melexis Microelectronic Systems – 300 to 930MHz FSK/FM/ASK Receiver

MLX71122
300 to 930MHz FSK/FM/ASK Receiver
Datasheet
MFO
[11:8]
multi functional output
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Z state
SPI read-out
MFO = 0
MFO = 1
analog RO output
analog IFF output
resistor (for test purposes)
resistor (for test purposes)
lock detect output
N divider output (for test purposes)
R divider output (for test purposes)
CCO output (for test purposes)
prescaler MC bit output with SCLK as clock (for test)
N divider output with SCLK as clock (for test)
R divider output with SCLK as clock (for test)
RIFF output with SCLK as clock (for test)
#default
4.1.5. Control Word R4
Name
R
AGCMODE
Bits
[10:0]
[11]
Description
reference divider range
000 0100 1011 value is 75
R counter range: 3 to 2047
AGC delay mode
0 gain decrease and increase with delay
1 _{gain decrease without delay, gain increase with delay}
selects AGC delay mode in combination with AGCDEL bits, see section 4.1.4 (R3)
#default
#default
4.1.6. Control Word R5
Name
RIFF
MODSEL
Bits
[10:0]
[11]
Description
reference divider value for IFF adjustment
010 1010 1100 value is 684
IFF counter range: 4 to 2047
demodulation selection
0 FSK demodulation
1 _{ASK demodulation}
selects modulation type when chip is controlled via SPI mode
#default
#default
REVISION 014 – AUGUST, 2016
390 10 71122 01
Page 44 of 59