MLX71122_16 Datasheet, PDF (34/59 Pages) Melexis Microelectronic Systems – 300 to 930MHz FSK/FM/ASK Receiver

MLX71122
300 to 930MHz FSK/FM/ASK Receiver
Datasheet
3.4.2. Averaging Data Slicer Mode
The averaging data slicer mode is the default setting for the data path of the MLX71122. Bit SLCSEL in
register R0 (see 4.1.1) is LOW if it is active and switch SW2 connects the pin SLC with DFO via a 200k
resistor (see Fig. 1). With an external capacitor C10 at pin SLC, a simple low pass filter is formed that
generates the threshold voltage for the output comparator. The value of C10 depends on the length of the
packet preamble, the coding and the data rate. The larger the C10 value the longer the time until valid
output data can be received at pin DTAO.
Averaging data slicer mode can be used for bi-phase or Manchester encoded bit streams since the DC-
content of these codes is almost zero. The RC-time constant of the slicer can be calculated using:
t_SLC  200kΩ  C10
(26)
We recommend that t_SLC is at least 25 times as long as the bit time of the equivalent NRZ signal.
Example: base band signal 4kbps, NRZ coding
C10  ^{25 0.25ms}  31.25nF
200kΩ
in E-series  C10  33nF
3.4.3. Peak Detectors (PKDET)
Peak detector mode is recommended for fast acquisition of the received data and if NRZ code is used. We
recommend turning off the IFF auto tuning after the PLL lock during FSK-reception in peak detector mode.
The peak detectors can be activated by setting SLCSEL to HIGH in register R0 (see 4.1.1). This connects SLC
(pin 32) with the resistive voltage divider between PDP (pin 25) and PDN (pin 26) (see Fig. 1). The peak
detector at PDP is used to detect the maximum of the voltage at DFO and the peak detector at PDN
detects the minimum of the voltage at DFO. Since the voltage divider is symmetric, the threshold voltage
will be in the middle of the minimum and maximum voltages at DFO. The peak voltages are proportional to
the charge that is stored on the peak detector capacitors at PDP (C11) and PDN (C12). All pull-up and pull-
down currents are given in sec. 5.5. Because both pins are connected via a 2M resistor, both peak
detector capacitors will be discharged with a time constant depending on the value of the capacitors. For
equal values of both capacitors (C = C11 = C12), the time constant will be:
t_DIS  2MΩ  0.5  C
(27)
The minimum value of t_DIS is limited by the maximum number of equal consecutive bits. A value of t_DIS of at
least 4 times the number of equal consecutive bits is a good choice.
Example: base band signal 4kbps, NRZ coding, max. 32 equal consecutive bits
C11  C12  ^{32  4  0.25ms}  32nF
0.5  2MΩ
in E-series  C11  C12  33nF
The maximum capacitor value may also be limited by the pull-up and pull-down currents of the peak
detectors given in sec. 5.5, because C11 and C12 have to be charged during the first bits of the preamble of
the data packet. The capacitors C11 and C12 are discharged if the circuit is powered but not in receive
mode (see 3.8). The capacitor C11 will be pre-charged with ground potential and C12 will be pre-charged
with VCC potential in order to prepare the peak data slicer circuit for fast output of valid data.
REVISION 014 – AUGUST, 2016
390 10 71122 01
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