MLX71122_16 Datasheet, PDF (25/59 Pages) Melexis Microelectronic Systems – 300 to 930MHz FSK/FM/ASK Receiver

MLX71122
300 to 930MHz FSK/FM/ASK Receiver
Datasheet
A good source for a detailed PLL analysis is: “Gardner, F.M., Phase-Locked Loop Techniques, John Wiley &
Sons, 1980.”
VCC
CF1
RF
CF2
LF
+
VCO
Fig. 8: 2^nd order Loop filter
3.2.7. Lock Detector (LD)
In SPI mode a lock-detect signal LD is available at pin 23 if MFO is set to 1000 (binary) in control word R3
(see 4.1.4). The pin output is HIGH when the PLL is locked in. Alternatively the lock-detect signal is visible in
bit 10 of R7 (see 4.1.8) if bit SHOWLD in R1 (see 4.1.2) is HIGH. The lock detection circuitry uses the Up and
Down signals from the phase-frequency detector to check them for phase coherency. Figure 9 shows an
overview of the lock signal generation. The locked state and the unlock condition will be controlled by the
register settings of LDTIME and LDERR. During the start-up phase of the PLL, Up and Down signals are quite
unbalanced. Therefore the Lock Detector circuit waits the time span that is programmed in divider
DIV_LDTIME before a first lock can occur. The time span is dependent on the period of the reference signal
f_R. By default it is 16/f_R (see 4.1.2). When the PLL approaches steady state, the signals Up and Down begin
to overlap. The time span within which the signals are not overlapping is assessed by using a
programmable delay gate. If it is shorter than programmed in LDERR (see 4.1.2) then the LD output is set
to HIGH. By default the error time should be shorter than 15ns. A second option is shorter than 30ns.
After LD is set to HIGH the divider is disabled and the lock state remains unchanged until the unlock signal
resets the divider.
LDTIME [1:0 ] ²
DIV_LDTIME
2
O
LD
4
8
f_R
>1
C
16
R
MUX
1
EN
U_p
=1
D_n
=
15ns
30ns
delay
>1
1
>1 R Q unlock
&
S
LDERR
LDMODE
Fig. 9: Lock Detection Circuit
REVISION 014 – AUGUST, 2016
390 10 71122 01
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