MLX71122_16 Datasheet, PDF (23/59 Pages) Melexis Microelectronic Systems – 300 to 930MHz FSK/FM/ASK Receiver

MLX71122
300 to 930MHz FSK/FM/ASK Receiver
Datasheet
A cycles of f _P
period of f_P
(N-A) cycles of f _P
Fig. 6 Pulse Swallow Divider Timing
Therefore the overall feedback divide ratio is:
P 1 A  P  N  A  N  P  A .
(16)
Further restrictions can be derived from above equation: A < P and A < N.
Some math shows that for uniform frequency steps without gaps (N ≥ P) the following condition is
necessary:
NPA PP.
(17)
3.2.2. PLL Counter Ranges
In order to cover the frequency range of about 300 to 930MHz the following counter values are
implemented in the receiver:
PLL Counter Ranges
A
N
R
P
0 to 31 (5bit)
3 to 2047 (11bit)
3 to 2047 (11bit)
32
Therefore the minimum and maximum divider ratios for uniform frequency steps are given by:
N_totmin  32  32  1024
N_totmax  2047  32  31  65535
3.2.3. Reference Oscillator (RO)
The reference oscillator is based on a Colpitts topology with two
integrated functional capacitors as shown in figure 7. The circuitry is
optimized for a load capacitance range of 10pF to 15pF. The equivalent
input capacitance CRO offered by the oscillator input pin ROI is about
15pF. To ensure a fast and reliable start-up and a very stable frequency
over the specified supply voltage and temperature range, the oscillator
bias circuitry provides an amplitude regulation. Via SPI it is possible to
adjust the typical core current with register ROCUR. There are four
values available (see 4.1.7). At the default setting 355A, the
amplitude at pin ROI is monitored in order to regulate the current of
the oscillator core I_RO.
VCC
ROI
30pF
CX
XTAL
VEE
I_RO
30pF
Fig.7: RO schematic
REVISION 014 – AUGUST, 2016
390 10 71122 01
Page 23 of 59