MLX71122_16 Datasheet, PDF (22/59 Pages) Melexis Microelectronic Systems – 300 to 930MHz FSK/FM/ASK Receiver

MLX71122
300 to 930MHz FSK/FM/ASK Receiver
Datasheet
A
f _FB
floor (x)
f _PFD
f _RO
R
 f_R
f _RO
f _VCO
N_tot  N  P  A
N
N _LO2
P
R
List of Mathematical Acronyms
divider ratio of the swallow counter (part of feedback divider)
frequency at the feedback divider output
The floor function gives the largest integer less than or equal to x.
For example, floor(5.4) gives 5, floor(-6.3) gives -7.
PFD frequency in locked state
reference frequency of the PLL
frequency of the crystal reference oscillator
frequency of the VCO (equals the LO1 signal of the first mixer)
total divider ratio of the PLL feedback path
divider ratio of the program counter (part of feedback divider)
LO2DIV divider ratio, to derive the LO2 signal from LO1 (N₁ = 4 or 8)
divider ratio of the prescaler (part of feedback divider)
divider ratio of the reference divider R
3.2.1. Pulse Swallow Counter
The programmable feedback divider of the PLL is based on a pulse-swallow topology. Fig. 5 depicts its
implementation, consisting of a dual-modulus prescaler, an RS latch and two programmable counters.
VCO
f _VCO
Dual Modulus
Prescaler
P / P+1
Program
Counter
f_P
N
f _FB
PFD
Modulus Control
Signal (MC)
QR
RS
LATCH
S
f
FB
=
N
f
VCO
P+
A
MC Mode
0 P+1
1
P
A
Swallow
Counter
Fig. 5 Pulse Swallow Counter Topology
During one cycle of f_FB the prescaler begins the operation by dividing by P+1 until the swallow counter A is
full. The RS latch is then set and changes the prescaler modulus to P (via the modulus control signal MC)
and disables the swallow counter. The division process continues until the program counter N is full and
the RS latch is reset.
REVISION 014 – AUGUST, 2016
390 10 71122 01
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