MLX71122_16 Datasheet, PDF (24/59 Pages) Melexis Microelectronic Systems – 300 to 930MHz FSK/FM/ASK Receiver

MLX71122
300 to 930MHz FSK/FM/ASK Receiver
Datasheet
3.2.4. Phase-Frequency Detector (PFD)
The phase-frequency detector (in conjunction with the charge pump) generates a voltage step at the loop
filter pin LF. This voltage step is proportional to the phase difference between the digital input signals f_R
and f_FB. The implementation of the phase detector is phase-frequency type. This circuitry is very useful
because it decreases the acquisition time significantly even if both frequencies differ very much. The
phase-frequency detector creates Up and Down signals that control the charge pump and that are also
used for the lock de-tection circuit. The first rising edge of one of the input signals, after a reset of Up and
Down, sets either the Up or the Down signal from LOW to HIGH. The following rising edge of the other
signal resets Up and Down. If the register setting PFDPOL (see 4.1.2) is HIGH, the PFD polarity is positive.
This means a rising edge of the signal f_R sets Up from LOW to HIGH and a rising edge of the signal f_FB sets
Down from LOW to HIGH. If PFDPOL is LOW, the PFD polarity is negative and the assignment of Up and
Down to the signals f_R and f_FB is swapped.
In the MLX71122 receiver the VCO frequency increases if the loop filter output voltage increases and vice
versa. The PFD polarity needs to be positive to achieve the correct feedback in the PLL loop. If an external
varactor diode is added to the VCO tank, the tuning characteristic may change from positive to negative
depending on the particular varactor diode circuitry. Therefore the PFDPOL bit can be used to define the
phase-frequency detector polarity.
3.2.5. Charge Pump (CP)
The Charge Pump is controlled by the Up and Down signals of the Phase-Frequency Detector. If the Up
signal is HIGH, then the charge pump current I_CP is sourced from the positive supply rail to the loop filter
pin LF (pin 15). If the Down signal is HIGH, then the current I_CP is drained from pin LF to ground.
The gain of the phase detector in conjunction with the charge pump can be expressed as:
K_PD 
I_CP
2π
,
(18)
whereas I_CP is the charge pump current which is set via register CPCUR (see 4.1.2). Default of I_CP is 100A.
The static Up and Down selections of I_CP can be used for test purposes.
3.2.6. Loop Filter (LF)
Since the loop filter has a strong impact on the function of the PLL, it must be chosen carefully. The
suggested filter topology is shown in Fig. 8.
The loop filter of the PLL is set up by an external resistor and two external capacitors. It constitutes a 2nd
order passive filter. This approach allows the user to easily adapt the loop filter bandwidth to different
requirements. As a rule of thumb the loop filter bandwidth of an integer-N PLL should be set 10 times
smaller than the PFD frequency. This is to achieve a stable PLL with a flat VCO noise floor.
The loop filter bandwidth depends on the external resistor and capacitors as well as on the VCO gain, the
charge pump current and the so-called phase margin. A phase margin of 45° is commonly used for highest
PLL stability. It is recommended to follow the component lists of section 6 for choosing appropriate values
of the loop filter resistor and capacitors.
REVISION 014 – AUGUST, 2016
390 10 71122 01
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