MAX11270 Datasheet, PDF (9/46 Pages) Maxim Integrated Products – Integrated PGA

MAX11270
24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma
ADC with Integrated PGA
Electrical Characteristics (continued)
(V_AVDD = 3.6V, V_AVSS = 0V, V_DVDD = 2.0V, V_REFP = 2.5V, V_REFN = 0V; f_DATA = 1000sps, External Clock = 8.192MHz; Continuous
conversion mode (SCYCLE = 0); PGA maximum output is 300mV below AVDD and minimum output is 300mV above AVSS,
T_A = T_MIN to T_MAX, unless otherwise noted. Typical values are at T_A = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
SPI TIMING REQUIREMENTS (See Figures 4–7)
SCLK Frequency
f_SCLK
SCLK Clock Period
t_CP
200
SCLK Pulse Width High
t_CH
Allow 40% duty cycle
80
SCLK Pulse Width Low
t_CL
Allow 40% duty cycle
80
CSB Low Setup
t_CSS0 CSB low to 1st SCLK rise setup
40
5
MHz
ns
ns
ns
ns
Required to prevent a 17th SCLK RE from
CSB High Setup
t_CSS1 being recognized by the device in a free-
40
ns
running application
CSB Hold
CSB Pulse Width
DIN Setup
DIN Hold
DOUT Transition
DOUT Hold
t_CSH1
SCLK falling edge to CSB rising edge,
CSB hold time
3
t_CSW Minimum CSB pulse width high
40
t_DS
DIN setup to SCLK rising edge
40
t_DH
DIN hold after SCLK rising edge
0
t_DOT
DOUT transition valid after SCLK fall
t_DOH
Output hold time remains valid after SCLK
fall
3
ns
ns
ns
ns
40
ns
ns
DOUT Disable
CSB Fall to DOUT Valid
t_DOD
CSB rise to DOUT disable,
CLOAD = 20pF
Default value of DOUT is ‘1’ for minimum
t_DOE
specification, max specification for valid ‘0’
0
on RDYB
25
ns
40
ns
SCLK Fall to RDYB ‘1’
RDYB transitions from ‘0’ to ‘1’ on falling
t_R1
edge of SCLK after LSB of DATA is shifted
0
onto DOUT
40
ns
RSTB Fall or SYNC Rise to
RDYB ‘1’
RDYB transitions from ‘0’ to ‘1’ on falling
t_R2
edge of RSTB or rising edge of SYNC
after 2 f_CLK cycles
Minimum SYNC High Pulse
Width
t_SYNC1
2
Minimum RSTB Low Pulse
Width
t_RSTB0
2
2
1/f_CLK
1/f_CLK
1/f_CLK
Note 2: Limits are 100% production tested at T_A = +25°C. Limits over the operating temperature range are guaranteed by design
and device characterization.
Note 3: Noise-free resolution is defined using the peak-to-peak input range and the peak-to-peak noise voltage. The peak-to-peak
noise voltage is defined as the RMS noise voltage times 6.6.
Note 4: These specifications are not fully tested and are guaranteed by design and/or characterization.
Note 5: Reference common mode (V_REFP + V_REFN)/2 ≤ (V_AVDD + V_AVSS)/2 +0.1V.
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