MAX11270 Datasheet, PDF (24/46 Pages) Maxim Integrated Products – Integrated PGA

MAX11270
24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma
ADC with Integrated PGA
Digital Filters
The digital filter is a mode-configurable digital filter and
decimator that processes a one-bit data stream from the
fourth order delta-sigma modulator and implements a fifth
order SINC function with an averaging function to produce
a 24-bit wide data stream. The internal state machine
runs synchronous with the system clock of 8.192MHz.
SINC Filter
The SINC filter allows MAX11270 to achieve very high
SNR. One feature of the fifth order SINC filter is a band-
width that is about twenty percent of the data rate. The
following example shows 3dB BW of about 3kHz for
16ksps data rate.
Serial Interface
The MAX11270 interface is fully compatible with SPI,
QSPI™, and MICROWIRE®-standard serial interfaces.
The SPI interface provides access to on-chip registers
that are 8 bits to 24 bits wide.
Chip Select (CSB)
CSB is an active-low chip-select input to communicate
with the MAX11270. CSB transitioning from low to high
is used to reset the SPI interface. When CSB is low, data
is clocked into the device from DIN on the rising edge of
SCLK. Data is clocked out of DOUT on the falling edge of
SCLK. When CSB is high, SCLK and DIN are ignored and
DOUT is high impedance allowing DOUT to be shared
with other devices.
SCLK (Serial Clock)
The serial clock (SCLK) is used to synchronize data com-
munication between the host device and the MAX11270.
Data is shifted in on the rising edge of SCLK and data is
shifted out on the falling edge of SCLK. SCLK remains
low when not active.
DIN (Serial Data Input)
Data present on DIN is clocked into internal registers on
the rising edge of SCLK.
QSPI is a trademark of Motorola, Inc.
MICROWIRE is a registered trademark of National Semiconductor Corp.
Figure 3a. SINC Magnitude Response
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Figure 3b. SINC Mag Response Zoomed-In
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