 English |
|
|
|
|
|
|
|
| MAX11270 Datasheet, PDF (7/46 Pages) Maxim Integrated Products – Integrated PGA | |||
| |||
| ◁ |
MAX11270
24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma
ADC with Integrated PGA
Electrical Characteristics (continued)
(VAVDD = 3.6V, VAVSS = 0V, VDVDD = 2.0V, VREFP = 2.5V, VREFN = 0V; fDATA = 1000sps, External Clock = 8.192MHz; Continuous
conversion mode (SCYCLE = 0); PGA maximum output is 300mV below AVDD and minimum output is 300mV above AVSS,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
ANALOG INPUTS/REFERENCE INPUTS
CONDITIONS
AIN Voltage Range
VRNG
Unipolar
Bipolar
Bypass mode
Absolute Input Voltage
VABSRNG PGA mode
Buffer mode
AIN DC Input Leakage
(Note 4)
AIN Common-Mode Input
Conductance
AIN Common-Mode Input
Current
AIN Differential Mode Input
Conductance
AIN Differential Mode Input
Current
REF Differential Input
Conductance
REF Input Current at Power
Down
AIN Input Capacitance
REF Input Capacitance
Input and REF Sampling
Rate
IINLEAK Sleep mode enabled
GAINCM Bypass
IAINCM
Buffer
PGA
GAINDIFF Bypass
IAINDIFF
Buffer
PGA
GREFDIFF Active conversion state
IREF_PD
CIN
CREF
fS
Sleep and Standby states
Buffer disabled
Buffer disabled
VREFP - VREFN Voltage
Range
VRABSRNG (Note 5)
REF Voltage Range
DIGITAL FILTER RESPONSE
VREF
SINC FILTER
Bandwidth (-3dB)
Settling Time (Latency)
BWSINC
MIN
TYP
MAX UNITS
0
-VREF
VAVSS
VAVSS
+ 0.3
VAVSS
+ 0.1
-10
VREF
V
VREF
VAVDD
VAVDD
- 1.3
V
VAVDD
- 0.1
+10
nA
±8
±500
±21
±23
±20
±0.15
±46.5
nA/V
nA
nA
µA/V
nA
nA
µA/V
±2.5
3
4.5
4.096
µA/V
pF
pF
MHz
VAVDD
V
1.5
VAVDD
V
0.203
5
fDATA
1/fDATA
www.maximintegrated.com
Maxim Integrated ââ 7
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese