MAX11270 Datasheet, PDF (18/46 Pages) Maxim Integrated Products – Integrated PGA

MAX11270
24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma
ADC with Integrated PGA
Table 1. Continuous Mode SNR (dB) vs Data Rate and PGA Gain with Sinc Filter^*
DATA
RATE
(sps)
1.9
3.9
7.8
15.6
31.2
62.5
125
250
500
1000
2000
4000
8000
16000
32000
64000
129.8
129.8
129.4
129.3
125.5
123.4
119.9
117.9
114.1
112.0
108.1
106.1
102.2
100.2
96.2
94.2
130.2
129.9
129.8
129.5
125.6
123.6
119.9
118.0
114.2
112.1
108.2
106.2
102.3
100.3
96.3
94.2
1
LN LP
128.8 128.7
128.6 128.5
128.4 128.3
128.2 128.2
124.4 124.2
122.3 122.1
118.7 118.6
116.7 116.7
113.0 112.9
110.9 110.8
106.9 106.9
104.9 104.9
101.0 101.0
99.0 99.0
95.1 95.1
93.0 92.9
2
LN LP
130.0 129.5
130.1 129.9
129.9 129.6
129.5 129.5
125.7 125.5
123.6 123.4
120.0 120.0
118.0 118.0
114.2 114.2
112.2 112.2
108.3 108.3
106.2 106.2
102.4 102.4
100.3 100.4
96.4 96.4
94.3 94.4
PGA ENABLED: GAIN SETTING
4
8
16
32
LN LP LN LP LN LP LN LP
129.8 129.8 130.0 130.0 129.7 129.7 130.0 129.5
130.0 129.7 129.9 129.7 129.4 129.4 129.6 128.8
129.7 129.6 129.5 129.5 129.5 129.3 128.6 127.7
129.6 129.5 129.2 129.0 128.7 127.8 127.9 126.5
125.7 125.5 125.2 125.2 124.9 124.7 123.9 123.5
123.5 123.5 123.2 123.2 122.8 122.7 121.6 121.2
119.9 119.9 119.7 119.7 119.4 119.3 118.4 117.8
117.9 117.9 117.7 117.8 117.3 117.1 116.1 115.4
114.1 114.1 114.0 114.0 113.6 113.5 112.6 112.0
112.0 112.0 111.9 111.9 111.5 111.2 110.3 109.5
108.2 108.2 108.1 108.1 107.8 107.5 106.8 106.1
106.1 106.1 106.0 106.0 105.6 105.3 104.5 103.8
102.3 102.3 102.2 102.2 102.0 101.7 101.2 100.6
100.3 100.3 100.2 100.2 100.0 99.9 99.4 99.0
96.3 96.4 96.3 96.3 96.2 96.0 95.7 95.3
94.2 94.2 94.2 94.2 94.1 93.9 93.6 93.2
64
LN LP
128.7 127.6
127.9 126.9
126.6 125.4
124.8 123.4
121.3 120.2
118.8 117.5
115.7 114.3
113.1 111.6
110.0 108.4
107.3 105.7
104.2 102.6
101.8 100.2
99.0 97.6
97.5 96.3
94.1 93.0
91.9 90.8
128
LN LP
126.1 124.0
124.3 122.6
122.3 120.2
119.7 117.0
116.6 114.7
113.8 111.9
110.8 108.8
108.0 105.9
105.0 102.9
102.2 100.0
99.2 97.1
96.7 94.6
94.4 92.4
93.2 91.3
90.2 88.4
87.9 86.2
*V_IN = 0V. V_AVDD = 3.6V, V_AVSS = 0V, V_REF = 3.6V, T_A = +25°C, external clock. Data taken with PGA output 150mV from AVDD
and AVSS. This table is not tested and is based on characterization data.
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