MAX11270 Datasheet, PDF (29/46 Pages) Maxim Integrated Products – Integrated PGA

MAX11270
24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma
ADC with Integrated PGA
Modes and Registers
The MAX11270 interface operates in two modes, conversion mode or register access mode, which is selected by the
command byte. Every SPI transaction to the MAX11270 starts with a command byte. The command byte begins with a
START bit (B7), which must be set to 1. The next bit is the MODE bit (B6), which selects between conversion mode or
register access mode. Based on the mode selection the remaining bits in the command byte get decoded accordingly.
If the command byte is for a register read/write request, hold CSB low for the entire read or write operation and pull CSB
high at the end of the command. For example, if the command is to read a 24-bit data register; hold CSB low for 32 SCLK
cycles (8 cycles of command plus 24 cycles of data). CSB transitions must not occur near the rising edge of SCLK and
must conform to the setup and hold timing detailed in the timing section.
Pulling CSB from low to high ends the current SPI transaction. If CSB is pulled high in the middle of a register write com-
mand, the registers will retain any partially written data. This does not cause a change in state of any internal register
that was being accessed for read or write
Conversion Mode (MODE = 0)
Table 6. Command Byte for Conversion Modes (MODE = 0)
BIT
B7 (MSB)
B6
B5
BIT NAME START = 1 MODE = 0
CAL
B4
IMPD
B3
RATE3
B2
RATE2
B1
RATE1
B0
RATE0
Set the MODE bit to 0 to: start a conversion with a rate defined by RATE[3:0], immediately power down the part or per-
form a calibration.
The CAL bit (B5) determines if a calibration is to be performed. Set CAL = 1 to perform a calibration, for all other opera-
tions set CAL = 0. The calibration is done based on the setting of the calibration bits CTRL 5. Also see discussion on
calibration in the following sections.
The IMPD bit (B4) controls the software power-down. Set IMPD = 1 to power down the MAX11270 and enter sleep mode
or standby mode, based on the setting of the PD Bits in CTRL1, once the command byte is complete. The power-down
status does not change until another command byte is received that is interpreted as a conversion byte (MODE = 0, IMPD
= 0). Set IMPD = 0 for normal operation.
The data rate bits RATE[3:0] determine the conversion speed. Samples rates between 1.9sps to 16ksps are program-
mable via the RATE bits. The speed table is shown later in Table 7.
Register Access Mode (MODE = 1)
Table 7. Command Byte for Register Access Mode (MODE = 1)
BIT
B7 (MSB)
B6
B5
B4
B3
B2
B1
B0
BIT NAME START =1 MODE = 1
RS4
RS3
RS2
RS1
RS0
R/W
MODE 1 or Register Access Mode is used for reading from and writing to the registers of the MAX11270. Set the MODE
bit (B6) = 1 to configure the command byte for Register Access Modes.
The bits RS[4:0] determine the register that is addressed as shown in Table 6.
The R/W bit enables either a read or a write of the register. Set R/W = 0 to write to the selected register and R/W = 1 to
read from the selected register.
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