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MAX11270 Datasheet, PDF (8/46 Pages) Maxim Integrated Products – Integrated PGA
MAX11270
24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma
ADC with Integrated PGA
Electrical Characteristics (continued)
(VAVDD = 3.6V, VAVSS = 0V, VDVDD = 2.0V, VREFP = 2.5V, VREFN = 0V; fDATA = 1000sps, External Clock = 8.192MHz; Continuous
conversion mode (SCYCLE = 0); PGA maximum output is 300mV below AVDD and minimum output is 300mV above AVSS,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
LOGIC INPUTS
Input Current
Input Low Voltage
Input High Voltage
Input Hysteresis
GPIO Input Low Voltage
GPIO Input High Voltage
GPIO Input Hysterisis
LOGIC OUTPUTS
ILEAK_DIG Leakage current only
VIL
VIH
VHYS
VIL_GPIO
VIH_GPIO
VHYS_GPIO
-1
0.7x
VDVDD
1.0
+1
µA
0.3x
VDVDD
V
V
200
mV
0.4
V
V
20
mV
Output Low Level
Output High Level
Floating State Leakage
Current
VOL
VOH
IOL = 1mA
IOH = 1mA
IDIGO_LEAK
0.9x
VDVDD
-10
0.4
V
V
+10
µA
Floating State Output
Capacitance
CDIGO
9
pF
POWER REQUIREMENTS
Analog Negative Supply
VAVSS For split supplies, VAVSS = - VAVDD
-1.8
0
V
Analog Positive Supply
Digital Supply
VAVDD
VDVDD
For split supplies, VAVDD = - VAVSS
VAVSS +
2.7
2.0
VAVSS +
3.6
V
3.6
V
AVDD Sleep Current
IAVDD_SLEEP
0.9
3
µA
AVDD Standby Current
IAVDD_STBY
1.5
3
µA
DVDD Sleep Current
IDVDD_SLEEP
0.25
1
µA
DVDD Standby Current
Analog Supply Current
DVDD Operating Current
IDVDD_STBY
IAVDD
IDVDD
Bypass mode
Buffers mode
PGA low-power mode
PGA low-noise mode
SINC filter
21
200
µA
2.4
3.0
2.8
3.5
mA
3.6
5.0
4.4
6.0
0.77
1.5
mA
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