MAX11270 Datasheet, PDF (38/46 Pages) Maxim Integrated Products – Integrated PGA

MAX11270
24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma
ADC with Integrated PGA
Request a system full-scale calibration by setting the CAL bit to 1 and the CTRL5:CAL[1:0] = 10 and connect a system
full-scale signal level to the input pins. The system full-scale calibration requires 100ms to complete, and the SGC
register contains values that correct for the chip full-scale value.
A third level of calibration allows a write to the internal calibration registers through the SPI interface to achieve any
digital offset or scaling with the following restrictions. The range of digital offset correction is ±V_REF/4. The resolution
of offset correction is 0.5 LSB. The range of digital gain correction is from 0.75 to 2. The resolution of gain is less than
1ppm.
SPI System Offset Calibration Register (SOC_SPI)
The system offset calibration register is a 24-bit read/write register. The data written/read to/from this register is clocked
in/out MSB first. The format is always in two’s complement. This register temporarily holds the system offset calibra-
tion value from the user. This value gets copied into the SOC_ADC register. The value written to this register remains
until it is overwritten. This value gets invalidated for calibration after a system-calibration operation is requested. Any
attempt to write to this register during an active calibration operation will be ignored.
ADC System Offset Calibration Register (SOC_ADC)
This is 24-bit read only register. There are two ways this register value is updated. One way is if a system offset calibra-
tion operation is requested. Another way is if a user writes a value to SOC_SPI register, the value will then get copied
into SOC_ADC from SOC_SPI.
The system offset calibration value is subtracted from each conversion result if NOSYSO = 0 in the CTRL5 register.
The system offset calibration value is subtracted from the conversion result after self-calibration, but before system
gain correction. It is also applied prior to the 1x or 2x scale factor associated with bipolar and unipolar modes.
SPI System Gain Calibration Register (SGC_SPI)
The system gain calibration register is a 24-bit read/write register. The data written/read to/from this register is clocked
in/out MSB first. The format is always in two’s complement format. This register temporarily holds the system gain
calibration value from the user. This value gets copied into the SGC_ADC register. The value written to this register
remains until it is overwritten. This value gets invalidated for calibration after a system-calibration operation is request-
ed. Any attempt to write to this register during an active calibration operation will be ignored.
ADC System Gain Calibration Register (SGC_ADC)
This is 24-bit read only register. There are two ways this register value is updated. One way is if a system offset calibra-
tion operation is requested. Another way is if a user writes a value to SGC_SPI register, the value will then get copied
into SGC_ADC from SGC_SPI.
The system gain calibration value is used to scale the offset-corrected conversion result if NOSYSG = 0 in the CTRL5
register. The system gain calibration value scales the gain corrected result by up to 2x or can correct a gain error of
approximately -50%. The amount of positive gain error that can be corrected is determined by modulator overload
characteristics which may be as much as +25%. The gain will be corrected to within 1ppm.
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