MAX11270 Datasheet, PDF (25/46 Pages) Maxim Integrated Products – Integrated PGA

MAX11270
24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma
ADC with Integrated PGA
DOUT (Serial Data Output)
The DOUT pin is actively driven when CSB is low and
high impedance when CSB is high. Data are shifted out
on DOUT on the falling edge of SCLK.
Data Ready (RDYB)
The RDYB output displays the conversion status. RDYB
is forced low when a conversion result is ready for read-
out and remains low until the user reads the conversion
result. RDYB returns high after SCLK is pulled high, fol-
lowing a complete read of the data register. RDYB also
resets high for 4 master clock cycles prior to DATA regis-
ter update (see Figure 4).
When the modulator is in one of the continuous operat-
ing modes and the part has either experienced a RESET,
SYNC, or POR event, then the RDYB pin will remain
high until the selected filter is settled. If the SINC filter is
selected then RDYB remains high for five t_CNV times and
afterwards data appears at each t_CNV.
The conversion status can also be determined by reading
the MSTAT bit in the STAT1 register.
SPI Incomplete Write Command Termination
In case of register writes, the register values get updated
every 8th clock cycle with a byte of data starting from the
MSB. A minimum of 16 SCLKs are needed to write the first
byte of data in a multibyte register or for an 8-bit register.
For example, a 24-bit register write requires 8 SCLKs for
register access byte and 24 SCLKs (data bits to be writ-
ten). If only 15 SCLKs were issued out of 32 expected,
the register value will not be updated. At least 16 SCLKs
are required to update the MSB byte. For example, when
the user issues a write command for a 24-bit register write
and terminates after 16 SCLKs, only the MSB byte, bits
23 to 16 of the register are updated. Bits 15 to 0 retain the
old value of the register.
CSB/SCLK/DIN
SCYCLE=’1',
CONTSC=’0',
RDYB
SCYCLE=’1',
CONTSC=’1',
RDYB
SCYCLE=’0',
CONTSC=’x',
RDYB
CONVERT COMMANDS
tCNV
tCNV
DATA NOT RETRIEVED
tCNV
DATA
RETRIEVED
5 tCNV tCNV
Figure 4. DATA Ready Timing for All Conversion Modes
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