MAX11270 Datasheet, PDF (31/46 Pages) Maxim Integrated Products – Integrated PGA

MAX11270
24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma
ADC with Integrated PGA
Status Register (Read Only)
The 16-bit status register is a read-only register that indicates the following: power-down status, if the modulator was
reset or overloaded, the data rate, overrange condition, when a measurement is in progress and when a measurement
is complete.
BIT
B15 B14 B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00
BIT NAME
DEFAULT
0
0
1
1
1
0
0
0
1
0
0
1
0
0
0
0
BIT DEFAULT
00
0
LABEL
RDY
FUNCTION
Ready bit. RDY = 1 when a new conversion result is available. A read of the DATA register
resets RDY = 0. The function of the RDY bit is redundant and is duplicated by RDYB pin.
01
0
MSTAT
Measurement status bit. MSTAT = 1 indicates that a conversion, self-calibration, or system
calibration is in progress and that the modulator is busy. When the modulator is not converting,
MSTAT = 0.
02
0
DOR
Data overrange bit. DOR = 1 indicates that the conversion result has exceeded the maximum
or minimum value and that the result has been clipped or limited to the maximum value. DOR
= 0 when the conversion result is within the full-scale range.
03
0
SYSGOR
System gain overrange bit. SYSGOR = 1 indicates that a system gain calibration was
overranged. The SGC calibration coefficient maximum value is 1.9999999.
04
1
05
0
06
0
07
1
RATE0
RATE1
RATE2
RATE3
Data rate bits. See Table 13. The RATE bits indicate the conversion rate that corresponds to
the result in the DATA register or the rate that was used for calibration coefficient calculation.
Note: RATE bits always show the rate of previous conversion and not the rate of the
conversion in progress.
08
0
AOR
Analog overrange bit. AOR = 1 when the modulator detects that the analog input voltage
exceeds 1.3 x full-scale range.
09
0
RDERR
Data read error bit. RDERR = 1 when new result is being written to the DATA register while
user is reading from the DATA register. RDERR = 0 otherwise.
10
0
PDSTAT0 ^{00: ADC is converting}
01: Device is fully powered down
10: In standby mode with modulator powered OFF but subregulator powered ON.
11
1
PDSTAT1 _{11: Reserved.}
12
1
—
—
13
1
—
—
14
0
ERROR Error bit. ERROR = 1 when CAL[1:0] bits are set to invalid setting of 11.
15
0
INRESET In reset bit. INRESET = 1 when software reset is initiated till the part exits reset mode.
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