MAX11270 Datasheet, PDF (37/46 Pages) Maxim Integrated Products – Integrated PGA

MAX11270
24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma
ADC with Integrated PGA
Table 10. ADC Output Code Data Format
CODE
TRANSITION
≥ FS
FS – 1 LSB
Midscale + 1 LSB
Midscale
Midscale - 1 LSB
ZS + 1 LSB
≤ ZS
ANALOG INPUT
(AINP - AINN) (V)
≥ V_REF
VREF x (1 – (1/2^N – 1))
VREF/2^N - 1
VREF/2^N
-VREF/2^N -1
-VREF x (1 – (1/2^N – 1))
≤ -V_REF
DIGITAL OUTPUT CODE (Hex)
OFFSET BINARY
TWO’s COMPLEMENT
32-BIT
24-BIT
32-BIT
24-BIT
FFFFFFFF
FFFFFF
7FFFFFFF
7FFFFF
FFFFFFFE
FFFFFE
7FFFFFFE
7FFFFE
80000001
800001
00000001
000001
80000000
800000
00000000
000000
7FFFFFFF
7FFFFF
FFFFFFFF
FFFFFF
00000001
000001
80000001
800001
00000000
000000
80000000
800000
N = number of data bits, 32 or 24.
V_REF = V_REFP - V_REFN.
Calibration
Two types of calibration are available: self-calibration and system calibration. Self-calibration is used to reduce the
MAX11270 gain and offset errors during changing operating conditions such as supply voltages, ambient temperature,
and time. System calibration is used to reduce the gain and offset of the entire signal path. This enables calibration of
board level components and the integrated PGA. System calibration requires the MAX11270 inputs to be reconfigured
for zero scale and full scale during calibration. See Figure 9 for details of the calibration signal flow.
The on-chip calibration registers are enabled or disabled by programming the NOSYSG, NOSYSO, NOSCG, and
NOSCO bits in the CTRL5 register. See Table 6
Self-Calibration
The self-calibration is an internal operation and does not disturb the analog inputs. Self-calibration is accomplished in two
independent phases, offset and gain. The first phase disconnects the inputs to the modulator and shorts them together
internally to develop a zero-scale signal. A conversion is then completed and the results are post-processed to generate
an offset coefficient which cancels all internally generated offsets. The second phase connects the inputs to the reference
to develop a full-scale signal. A conversion is then completed and the results are post-processed to generate a full-scale
coefficient, which scales the converters full-scale analog range to the full-scale digital range.
The entire self-calibration sequence requires two independent conversions, one for offset and one for full scale.
The conversion rate is 50sps which provides the lowest noise and most accurate calibrations. The self-calibration opera-
tion excludes the PGA. A system-level calibration is available in order to calibrate the PGA signal path.
The calibration operations are controlled with the CAL bit in the command byte. Request a self-calibration by setting
the CAL bit to 1, with the CTRL5:CAL[1:0] = 00. A self-calibration requires 200ms to complete, and both the SCOC and
SCGC registers contain the values that correct the chip output for zero scale and full scale.
System Calibration
This mode is used when board level components and the integrated PGA calibration is desired. A system calibration
requires the user to configure the input to the proper level for the calibration operation. The offset and full-scale system
calibrations are performed using separate command bytes by configuring the CTRL5:CAL [1:0] bits. The system offset
and system full scale require setting these CAL bits appropriately before issuing the calibration command byte.
Request a system zero-scale calibration by setting the CAL bit to 1 and the CTRL5:CAL[1:0] bit = 01 and connect a
system zero-level signal to the input pins. The system zero calibration requires 100ms to complete, and the SOC register
contains values that correct the chip zero scale.
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