MAX11270 Datasheet, PDF (17/46 Pages) Maxim Integrated Products – Integrated PGA

MAX11270
AINP
A1
R1
R2
R1
A2
AINN
Figure 1. PGA Structure
VAVDD
24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma
ADC with Integrated PGA
R3
CAPP
CCAPP/N
(C0G capacitor)
R3
CAPN
Input Voltage Range
The ADC input range is programmable for bipolar (-V_REF
to +V_REF) or unipolar (0 to V_REF) ranges. The U/B bit in
the CTRL1 register configures the MAX11270 for unipolar
or bipolar transfer functions. See Figure 2.
Noise Performance vs. Data Rate
The MAX11270 offers software-selectable output data
rates in order to optimize data rate and noise. The RATE
bits in the command byte determines the ADC’s output
data rate. The MAX11270 offers zero latency in single-
cycle conversion mode. Set SCYCLE = 0 in the CTRL1
register to run in continuous conversion mode and
SCYCLE = 1 for single-cycle conversion mode.
Single-cycle conversion mode gives an output result with
no data latency for up to 12.8ksps. In continuous conver-
sion mode, the maximum output data rate is 64ksps. In
continuous conversion mode, the output data requires
four additional 24-bit cycles to settle from an input step.
For optimal SNR vs. power, it is recommended to use
different PGA modes. For gain settings 8 and below, use
low-power PGA mode, for gain setting above 8, use low-
noise PGA mode.
ANALOG INPUTS
PGA OUTPUT
VAVDD – 0.3V
VAVDD – 1.3V
COMMON-MODE
INPUT VOLTAGE
INPUT VOLTAGE RANGE
OUTPUT VOLTAGE RANGE = GAIN
x INPUT VOLTAGE RANGE
≤ VREF
VAVSS + 0.3V
VAVSS
Figure 2. Usable Input and Output Common-Mode Range
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