MAX11008 Datasheet, PDF (8/67 Pages) Maxim Integrated Products – Dual RF LDMOS Bias Controller with Nonvolatile Memory

Dual RF LDMOS Bias Controller with
Nonvolatile Memory
MISCELLANEOUS TIMING CHARACTERISTICS (Note 15) (continued)
(DV_DD = +2.7V to +5.25V, AV_DD = +4.75V to +5.25V, V_DGND = V_AGND = 0, external V_REFADC = +2.5V, external V_REFDAC = +2.5V,
C_REF = 0.1µF, T_A = -40°C to +85°C, unless otherwise noted.)
PARAMETER
DAC Power-Up Time (External
Reference)
DAC Power-Up Time (Internal
Reference)
Acquisition Time (Internally Timed
in ADC Clock Modes 00 or 01)
Conversion Time (Internally
Clocked)
Delay to Start of Conversion Time
Temperature Conversion Time
(Internally Clocked)
SYMBOL
t_DPUEXT
CONDITIONS
t_DPUINT
t_ACQ
t_CONV Internally clocked, T_A = +25°C
t_CONVW (Note 23)
t_CONVT
MIN TYP MAX UNITS
2
µs
70
µs
0.6
µs
10
µs
1.3
µs
70
µs
Note 1: Output settles to within ±0.5% of final value.
Note 2: Total unadjusted errors are for the entire gate-drive channel including the 12-bit DAC, and the gate driver is measured at
the GATE1 and GATE2 outputs.
Note 3: V_{GATE_} = V_DD - 0.1. Measured from when OPSAFE1 or OPSAFE2 is set high.
Note 4: During power-on-reset, the output safe switch is closed. The output safe switch is opened under user software control.
Note 5: Guaranteed to be 11 bits linearly accurate.
Note 6: Offset nulled.
Note 7: The absolute range for analog inputs is from 0 to V_AVDD.
Note 8: Internal temperature-sensor performance is guaranteed by design.
Note 9: The MAX11008 and the external sensor are at the same ambient temperature. External sensor measurement error is tested
with a diode-connected 2N3904.
Note 10: Guaranteed monotonicity. Accuracy is degraded at lower V_REFDAC.
Note 11: SDA/DIN is an open-drain output only when in I²C mode. A1/DOUT is an open-drain output only when in SPI mode.
Note 12: Supply-current limits are valid only when digital inputs are set to DGND or supply voltage. Timing specifications are only
guaranteed when inputs are driven rail-to-rail.
Note 13: Shutdown supply currents are typically 0.4µA for AV_DD; maximum specification is limited by automated test equipment.
Note 14: All times are referred to the 50% point between V_IH and V_IL levels.
Note 15: Guaranteed by design. Not production tested.
Note 16: DOUT will go into three-state mode after the CS rising edge. Keep CS low long enough for the DOUT value to be sampled
before it goes to three-state.
Note 17: A master device must provide a hold time of at least 300ns for the SDA signal (referred to V_IL of the SCL signal) to bridge
the undefined region of SCL’s falling edge.
Note 18: t_R and t_F measured between 0.3 x DV_DD and 0.7 x DV_DD.
Note 19: C_B = total capacitance of one bus line in pF. For bus loads between 100pF and 400pF, the timing parameters should be
linearly interpolated.
Note 20: An appropriate bus pullup resistance must be selected depending on board capacitance.
Note 21: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
Note 22: When a command is written to the serial interface, the command is passed by the internal oscillator clock and executed.
There is a small synchronization delay before the new value is written to the appropriate register. If the serial interface
attempts to read the new value back before t_RDBK, the new data is not corrupted; however, the result of the read command
may not reflect the new value.
Note 23: This is the minimum time from the end of a command before CNVST should be asserted. The time allows for the data from
the preceding write to arrive and set up the chip in preparation for the CNVST. The time need only be observed when the
write affects the ADC controls. Failure to observe this time may lead to incorrect conversions (for example, conversion of
the wrong ADC channel).
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