MAX11008 Datasheet, PDF (57/67 Pages) Maxim Integrated Products – Dual RF LDMOS Bias Controller with Nonvolatile Memory

Dual RF LDMOS Bias Controller with
Nonvolatile Memory
Table 14b. Clamp-Mode Select Bits (ALMCLMP[1:0])
ALMCLMP1
0
0
1
1
ALMCLMP0
0
1
0
1
CLAMP MODE
ALARM CLAMP SELECT
Alarm report ^{If an alarm is triggered by a current or temperature conversion, the ALARM}
bit is set (1) in the alarm Flag register. No further action is taken.
Clamp gate The GATE_ output clamps to AGND immediately, independent of alarms.
Clamp gate on
alarm with clear
The GATE_ output is clamped to AGND in response to any alarm trip on the
corresponding channel. A subsequent ADC conversion, which shows the
alarm condition has been removed, clears the clamp condition
automatically.
Clamp gate on
alarm without
clear
The GATE_ output is clamped to AGND in response to any alarm trip on the
corresponding channel. The clamp does not clear automatically. If an alarm
is triggered, the 11 value is overwritten to 01, causing a permanent clamp
condition. A subsequent write to rest ALMCLMP[1:0] to 11 clears the clamp
condition.
Table 15. VSET Registers
DATA BITS
D[15:12]
D[11:0]
BIT NAME
Unused
VSET_[11:0]
NA = Not applicable.
RESET STATE
0000
NA
Unused bits.
VSET_ bits.
FUNCTION
Set OSCPD to 1 to power down the internal oscillator.
When the internal oscillator is powered down, all inter-
nal operations of the MAX11008 are suspended.
OSCPD automatically resets back to 0 when the next
command is received by the serial interface.
Powering down the oscillator and leaving the watchdog
oscillator powered up may allow the watchdog timer to
overflow. The overflow of the watchdog timer forces the
MAX11008 to reset, reinitialize, and transmit a pulse on
the ALARM output.
Set DAC_PD to 1 to power down DAC_ and PGA_.
Values can still be written to the DAC Input and Output
registers when DAC_ is powered down.
Load DAC Register (LDAC) (Write Only)
Write to the Load DAC register to transfer the contents
of the DAC input registers to the DAC output registers
(see Table 22). The Load DAC register is a write-only
register that executes when written to, but does not
have storage. This function facilitates the simultaneous
update of both DAC outputs. Set LDDACCH1 to 1 to
transfer the contents of the DAC1 Input register to the
DAC1 Output register. Set LDDACCH2 to 1 to transfer
the contents of the DAC2 Input register to the DAC2
Output register. Bits D[15:2] are don’t-care bits.
Message Register (MR) (Write Only)
Write to the Message register to place the MAX11008
into message mode (see the Message Mode section
and Table 23). MSGL[7:0] specifies the number of data
words (each data word is 16 bits long) to be read from
the EEPROM. The message read from the EEPROM is
between 1 and 256 words long. Write MSGL = 0 (deci-
mal) to request a message length of 1, MSGL = 255
(decimal) to request a message length of 256.
MSGA[7:0] specifies the starting address of the mes-
sage to be read from the EEPROM.
FIFO Register (FIFO) (Read/Write)
When in message mode or ADC monitoring mode, the
FIFO register is a read-only register (see Table 24). In
message mode, the specified EEPROM data words
(each data word is 16 bits long) are copied into the
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