MAX11008 Datasheet, PDF (6/67 Pages) Maxim Integrated Products – Dual RF LDMOS Bias Controller with Nonvolatile Memory

Dual RF LDMOS Bias Controller with
Nonvolatile Memory
SPI TIMING CHARACTERISTICS (Notes 14, 15, Figure 1)
(DV_DD = +2.7V to +5.25V, AV_DD = +4.75V to +5.25V, V_DGND = V_AGND = 0, external V_REFADC = +2.5V, external V_REFDAC = +2.5V,
C_REF = 0.1µF, T_A = -40°C to +85°C, unless otherwise noted.)
PARAMETER
SCLK Clock Period
SCLK High Time
SCLK Low Time
DIN to SCLK Rise Setup Time
DIN to SCLK Rise Hold Time
SCLK Fall to DOUT Transition
CS Fall to DOUT Enable
CS Rise to DOUT Disable
CS Rise or Fall to SCLK Rise
CS Pulse-Width High
Last SCLK Rise to CS Rise
SYMBOL
t_CP
t_CH
t_CL
t_DS
t_DH
t_DO
t_DV
t_TR
t_CSS
t_CSW
t_CSH
CONDITIONS
C_L = 30pF
C_L = 30pF
C_L = 30pF (Note 16)
MIN TYP MAX UNITS
62.5
ns
25
ns
25
ns
15
ns
0
ns
20
ns
50
ns
50
ns
12.5
ns
50
ns
0
ns
I²C SLOW-/FAST-MODE TIMING CHARACTERISTICS (Notes 14, 15, Figure 4)
(DV_DD = +2.7V to +5.25V, AV_DD = +4.75V to +5.25V, V_DGND = V_AGND = 0, external V_REFADC = +2.5V, external V_REFDAC = +2.5V,
C_REF = 0.1µF, T_A = -40°C to +85°C, unless otherwise noted.)
PARAMETER
SCL Clock Frequency
Bus Free Time Between a STOP
and START Condition
SYMBOL
f_SCL
t_BUF
CONDITIONS
MIN TYP MAX UNITS
0
400
kHz
1.3
µs
Hold Time (Repeated) for START
Condition
t_HD:STA
After this period, the first clock pulse is
generated
0.6
µs
Setup Time for a Repeated
START Condition
t_SU:STA
0.6
µs
SCL Pulse-Width Low
SCL Pulse-Width High
Data Setup Time
Data Hold Time
SDA, SCL Rise Time
SDA, SCL Fall Time
SDA Fall Time
Setup Time for STOP Condition
Capacitive Load for Each Bus
Line
t_LOW
t_HIGH
t_SU:DAT
t_HD:DAT
t_R
t_F
(Note 17)
Receiving (Note 18)
Receiving (Note 18)
t_F
Transmitting (Notes 18, 19)
t_SU:STO
C_B
(Note 20)
1.3
0.6
100
0.004
0
0
20 + 0.1
x C_B
0.6
µs
µs
ns
0.9
µs
300
ns
300
ns
250
ns
µs
400
pF
Pulse Width of Spikes
Suppressed by the Input Filter
t_SP
(Note 21)
50
ns
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