MAX11008 Datasheet, PDF (23/67 Pages) Maxim Integrated Products – Dual RF LDMOS Bias Controller with Nonvolatile Memory

Dual RF LDMOS Bias Controller with
Nonvolatile Memory
Register Address/Data Bytes (5-Byte Read Cycle)
A read cycle begins with the master issuing a START
condition followed by a 7-bit address, (see Figure 5
and Table 1) and a write bit (R/W = 0) to instruct the
MAX11008 interface that it is about to receive data.
Once the slave address is recognized and the write bit
is received, the MAX11008 (I²C slave) issues an ACK
by pulling SDA low for one clock cycle. The master
then sends the register address byte (command byte)
to the slave. The MSB of the register address byte is
the read/write bit for the destination register address of
the slave and must be set to 1 for a read cycle (see the
Register Address Map section). After this byte is
received, another acknowledge bit is sent to the master
from the slave. The master then issues a repeated
START (Sr) condition. Following a repeated START (Sr),
the master writes the slave address byte again with a
read bit (R/W = 1). After a third acknowledge signal
from the slave, the data direction on the SDA bus
reverses and the slave writes the 2 data bytes (the
contents of the register that was addressed in the pre-
vious command byte) to the master. Finally, the master
issues a NACK followed by a STOP condition (P), end-
ing the read cycle. Figure 11 shows a complete 5-byte
read cycle.
Default Read Cycle (3-Byte Read Cycle)
The MAX11008 2-wire interface has a unique feature for
read commands. To avoid the necessity of sending 2
slave address bytes in one read cycle (see the 5-byte
read cycle in Figure 11), the MAX11008 2-wire interface
recognizes a single slave address byte with a read bit
(R/W = 1). In this case, the interface outputs the con-
tents of the last read device register. This default read
feature is useful when the master must perform multiple
consecutive reads from the same device register.
Figure 11 shows a complete 3-byte read cycle.
MASTER TO SLAVE
SLAVE TO MASTER
5-BYTE READ CYCLE
1
7
11
8
1
7
11
8
S
SLAVE
ADDRESS
W A COMMAND BYTE
A Sr
SLAVE
ADDRESS
RA
DATA BYTE
1
8
A
DATA BYTE
11
N P OR Sr
NUMBER OF BITS
3-BYTE READ CYCLE
1
7
11
8
1
8
11
NUMBER OF BITS
S
SLAVE
ADDRESS
RA
DATA BYTE
A
DATA BYTE
N P OR Sr
Figure 11. 5-Byte and 3-Byte Read Cycle
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