MAX11008 Datasheet, PDF (19/67 Pages) Maxim Integrated Products – Dual RF LDMOS Bias Controller with Nonvolatile Memory

Dual RF LDMOS Bias Controller with
Nonvolatile Memory
Read Format
Use the following sequence to read 16 bits of data from
a MAX11008 register (see Figure 3):
1) Drive CS low to select the device.
2) Send the appropriate read command byte (see
Table 6 for the register address map). The com-
mand byte is clocked in on the rising edges of
SCLK.
3) Receive 16 bits of data. The first 4 bits of data are
always high. Data is clocked out on the falling edges
of SCLK.
4) Drive CS high.
I²C Serial Interface
Connect SPI/I2C to DGND to select the I²C interface. The
I²C serial interface consists of a serial data line (SDA)
and a serial clock line (SCL). The MAX11008 is I²C com-
patible within the DV_DD = 2.7V to 5.25V range. SDA and
SCL facilitate bidirectional communication between the
MAX11008 and the master at rates up to 400kHz for fast
mode and up to 3.4MHz for high-speed mode (HS
mode). See the Bus Timing and HS I²C Mode sections
for more information on data-rate configurations.
Figure 4 shows the 2-wire interface timing diagram. The
MAX11008 is a transmit/receive slave-only device, rely-
ing upon a master to generate a clock signal. The mas-
ter (typically a microcontroller) initiates data transfers
on the bus and generates the SCL signal to permit data
transfer.
CS
SCLK
DIN R/W C6 C5 C4 C3 C2 C1 C0 X X X X X X X X X X X X X X X X X X
DOUT
D15
D14 D13 D12 D11 D10 D9 D8
D7
D6 D5 D4 D3 D2 D1 D0
Figure 3. SPI Read Sequence
a) F/S-MODE I²C SERIAL INTERFACE TIMING
SDA
t_{SU, DAT}
t_LOW
t_{HD, DAT}
t_{SU, STA}
t_{HD, STA}
t_R
t_F
t_BUF
t_{SU, ST0}
SCL
S
t_HIGH
t_{HD, STA}
t_R
t_F
b) HS-MODE I²C SERIAL INTERFACE TIMING
SDA
t_{SU, DAT}
t_LOW
SCL
t_{HD, STA}
t_RCL
S
t_HIGH
t_{HD, DAT}
t_RCL
t_{SU, STA}
HS MODE
Sr
A
t_{HD, STA}
Sr
A
P
t_RDA
S
t_RDA
t_BUF
t_{SU, ST0}
t_RCL
P
S
F/S MODE
PARAMETERS ARE MEASURED FROM 30% TO 70%.
Figure 4. I²C Serial-Interface Timing Diagram
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