MAX11008 Datasheet, PDF (20/67 Pages) Maxim Integrated Products – Dual RF LDMOS Bias Controller with Nonvolatile Memory

Dual RF LDMOS Bias Controller with
Nonvolatile Memory
A master device communicates to the MAX11008 by
transmitting the proper slave address followed by a
command and/or data words. Each transmit sequence
is framed by a START (S) or repeated START (Sr) con-
dition and a STOP (P) condition. Each word transmitted
over the bus is 8 bits long and is always followed by an
acknowledge clock pulse.
The MAX11008 SDA and SCL drivers are open-drain
outputs, requiring a pullup resistor (750Ω or greater) to
generate a logic-high voltage (see the Typical
Application Circuits). Series resistors are optional for
noise filtering. These series resistors protect the input
stages of the MAX11008 from high-voltage spikes on
the bus line, and minimize crosstalk and undershoot of
the bus signals.
Bit Transfer
One data bit is transferred during each SCL clock
cycle. The data on SDA must remain stable during the
high period of the SCL clock pulse. Changes in SDA
while SCL is high are control signals (see the START
and STOP Conditions section). Both SDA and SCL idle
high when the I²C bus is not busy.
START and STOP Conditions
The master initiates a transmission with a START condi-
tion (S), which is a high-to-low transition on SDA while
SCL is high. The master terminates a transmission with
a STOP condition (P), which is a low-to-high transition
on SDA while SCL is high (see Figure 5). A repeated
START condition (Sr) can be used in place of a STOP
condition to leave the bus active and the mode
unchanged (see the HS I²C Mode section).
Acknowledge Bits and Not-Acknowledge Conditions
Data transfers are framed with an acknowledge bit
(ACK) or a not-acknowledge bit (NACK). Both the mas-
ter and the MAX11008 (slave) generate acknowledge
bits. To generate an acknowledge, the receiving device
must pull SDA low before the rising edge of the
acknowledge-related clock pulse (ninth clock pulse)
and keep it low during the high period of the clock
pulse (see Figure 6).
To generate a not-acknowledge condition, the receiver
allows SDA to be pulled high before the rising edge of
the acknowledge-related clock pulse, and leaves SDA
high during the high period of the clock pulse.
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data
transfer happens if a receiving device is busy or if a
system fault has occurred. In the event of an unsuc-
cessful data transfer, the bus master reattempts com-
munication at a later time.
S
SDA
Sr
P
SCL
Figure 5. START and STOP Conditions
S = START.
Sr = REPEATED START.
P = STOP.
S
SDA
SCL
Figure 6. Acknowledge Bits
1
2
NOT ACKNOWLEDGE
ACKNOWLEDGE
8
9
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