MAX11008 Datasheet, PDF(40/67 Page) Maxim Integrated Products – Dual RF LDMOS Bias Controller with Nonvolatile Memory

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MAX11008 Datasheet, PDF (40/67 Pages) Maxim Integrated Products – Dual RF LDMOS Bias Controller with Nonvolatile Memory

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Dual RF LDMOS Bias Controller with

Nonvolatile Memory

EEPROM

The MAX11008 features 4Kb of EEPROM capable of

storing up to 256 16-bit data words. The first 64 data

words of the EEPROM contain configuration data (see

Table 4) while the remaining 192 data words are pro-

grammable and used for storing temperature and APC

LUTs. The MAX11008 utilizes the LUT values to perform

gate voltage calculations (see the VGATE_ Output

Equation section). See the First-In-First-Out (FIFO), LUT

Streaming Mode, and Message Mode sections for more

information on how to program and read from the

EEPROM. See the Temperature/APC LUT Configuration

Registers section for information on how to configure

the LUTs and how values are retrieved from the LUTs

for VGATE_ calculations. See Table 5.

Nonvolatile Initialization Values

Upon power-on reset, the data contained within specif-

ic EEPROM locations is copied directly to correspond-

ing locations within the register address map

depending on the state of the magic number (see the

Magic Number section).

â¢ Locations 0x10â0x1F are directly copied to their cor-

responding locations within the register address

map.

â¢ Locations 0x2Câ0x33 are conditionally copied to

their corresponding locations within the register

address map. Set the MSB (labeled WCTRAM) to 1

for locations 0x2Câ0x33 to be copied to the register

address map (see Table 4a).

By correctly configuring the initialization values stored

within the EEPROM, the MAX11008 can automatically

enter VGATE_ compensation mode without the need for

a host processor. This autonomous operation is useful

in some application areas where a host controller is not

desired.

Changes made to the working registers during opera-

tion are volatile. To change a registerâs nonvolatile ini-

tialization value, the corresponding EEPROM location

must be written by the LUT streaming protocol.

Magic Number

The address location 0x37 of the EEPROM is referred

to as the magic address. If the magic address is pro-

grammed with the magic number (0xAA55), the values

stored in address locations 0x10â0x1F and 0x2Câ0x33

are loaded into the working registers (see the Register

Address Map section) during power-up initialization.

Address locations 0x10â0x1F are unconditionally

loaded into the working registers, whereas address

locations 0x2Câ0x33 are only loaded if bit D15

(WCTRAM) of the address is set to 1. If magic address

location 0x37 is not programmed with the magic num-

ber (0xAA55), the EEPROM is determined to be unpro-

grammed; the power-up initialization load is then

bypassed and the working registers default to their

power-on reset value.

LUT Values

The values stored within the LUT section of the

EEPROM are 16-bit signed (twoâs complement)

Table 4a. EEPROM Address Bit Map

HEX

MNEMONIC

EE_TH1

EE_TL1

EE_IH1

EE_IL1

EE_TH2

EE_TL2

EE_IH2

EE_IL2

EE_HCFIG

EE_ALMSCF

EE_SCFIG

EE_ALMHCF

EE_VSET1

EE_HIST_AP

EE_VSET2

EE_HIST_AP

EE_IDAC1

EE_IODAC1

EE_IDAC2

EE_IODAC2

EE_PGACAL

EE_ADCCON

EE_SSHUT

EE_LDAC

MAGIC NUMBER

EE_TLUT1

EE_ALUT1

EE_TLUT2

EE_ALUT2

TABLE

16a

16b

16a

16b

BIT 15

T1AVGCTL

T2AVGCTL

T1HIST3

T2HIST3

WCTRAM

POFF5

BIT 14

T1LIMIT2

T2LIMIT2

T1HIST2

T2HIST2

POFF4

BIT 13

T1LIMIT1

T2LIMIT1

T1HIST1

T2HIST2

POFF3

BIT 12

T1LIMIT0

T1HIST0

T2HIST0

POFF2

BIT 11

D11

FIFOSTAT

A2AVG

LDAC2

D11

POFF1

BIT 10

D10

ADCMON

T2AVG

TCOMP2

AVGMON

D10

POFF0

BIT 9

PG2SET1

A1AVG

APCCOMP2

INTEMP2

INT1

BIT 8

PG2SET0

T1AVG

TSRC2

ALMCMP

INT0

BIT 7

PG1SET1

TALARM2

APCSRC21

ALMHYST1

A1AVGCTL

A2AVGCTL

CONCONV

PSIZE1

BIT 6

PG1SET1

TWIN2

APCSRC20

ALMHYST0

A1LIMIT2

A2LIMIT2

ADCIN2

PSIZE0

BIT 5

CKSEL1

IALARM2

LDAC1

ALMCLMP21

A1LIMIT1

A2LIMIT1

CS2

TSIZE2

BIT 4

CKSEL0

IWIN2

TCOMP1

ALMCLMP20

A1LIMIT0

A2LIMIT0

EXTTEMP2

TSIZE1

BIT 3

ADCREF1

TALARM1

APCCOMP1

ALMCLMP11

A1HIST3

A2HIST3

ADCIN1

FBGON

TSIZE0

BIT 2

ADCREF0

TWIN1

TSRC1

ALMCLMP10

A1HIST2

A2HIST2

TRACK

CS1

OSCPD

SOT2

BIT 1

DACREF1

IALARM1

APCSRC11

ALMPOL

A1HIST1

A2HIST1

DOCAL

EXTEMP1

DAC2PD

DAC_CH2

SOT1

BIT 0

DACREF0

IWIN1

APCSRC10

ALMOPN

A1HIST0

A2HIST0

SELFTIME

INTEMP

DAC1PD

DAC_CH1

SOT0

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