MAX11008 Datasheet, PDF (63/67 Pages) Maxim Integrated Products – Dual RF LDMOS Bias Controller with Nonvolatile Memory

Dual RF LDMOS Bias Controller with
Nonvolatile Memory
Bypass the AV_DD supply with a 0.1µF capacitor to
AGND, and place the capacitor as physically close as
possible to the AV_DD input. Bypass the DV_DD supply
with a 0.1µF capacitor to DGND, and place the capacitor
as physically close as possible to the DV_DD input. If the
power supply is very noisy, connect a 10Ω resistor in
series with the supply input to improve power-supply fil-
tering.
Table 22. Load DAC Register
DATA BITS
D[15:2]
D1
BIT NAME
Unused
LDDACCH2
D0
LDDACCH1
X = Don’t care.
NA = Not applicable.
RESET STATE
X
Unused bits.
FUNCTION
NA
Channel 2 load DAC bit. Set to 1 to transfer DAC2 input register contents to
DAC2 output register.
NA
Channel 1 load DAC bit. Set to 1 to transfer DAC1 input register contents to
DAC1 output register.
Table 23. Message Register
DATA BITS
D[15:8]
D[7:0]
BIT NAME
MSGL[7:0]
MSGA[7:0]
RESET STATE
FUNCTION
0000 0000
Message length bits. Specifies the length of the message to be read from
the EEPROM in words. The actual length read is MSGL + 1.
0000 0000
Message address bits. Specifies the starting address of the message to be
read from the EEPROM.
Table 24. FIFO Read Register
DATA BITS
D[15:12]
D[11:0]
BIT NAME
DATA[15:12]/
TAG[3:0]
DATA[11:0]
RESET STATE
FUNCTION
0000
Message mode data bits/LUT streaming mode data bits/ADC channel tag
bits. See Table 24a.
0000 0000 0000 Message data bits/ADC data bits.
10mils
AGND TRACE
DXP_ TRACE
10mils
10mils
DXN_ TRACE
AGND TRACE
10mils
Figure 23. Recommended DXP_ and DXN_ PCB Trace Layout
______________________________________________________________________________________ 63