MAX11008 Datasheet, PDF (46/67 Pages) Maxim Integrated Products – Dual RF LDMOS Bias Controller with Nonvolatile Memory

Dual RF LDMOS Bias Controller with
Nonvolatile Memory
Table 6. Register Address Map
REGISTER
Channel 1 High Temperature Threshold
Channel 2 High Temperature Threshold
Channel 1 Low Temperature Threshold
Channel 2 Low Temperature Threshold
Channel 1 High Current Threshold
Channel 1 Low Current Threshold
Channel 2 High Temperature Threshold
Channel 2 Low Temperature Threshold
Hardware Configuration
Alarm Software Configuration
Software Configuration
Alarm Hardware Configuration
VSET1
VSET2
APC1 Parameter
APC2 Parameter
DAC1 Input (Write Only)
DAC2 Input (Write Only)
DAC1 Input and Output (Write Only)
DAC2 Input and Output (Write Only)
PGA Calibration Control ( Write Only)
ADC Conversion (Write Only)
Software Shutdown (Write Only)
Load DAC (Write Only)
Message (Write Only)
FIFO
Software Clear (Write Only)
LUT Streaming (Write Only)
Flag (Read Only)
MNEMONIC
SEE
TABLE
COMMAND BITS
HEX CODE
C7 C6 C5 C4 C3 C2 C1 C0 WRITE READ
TH1
TH2
TL1
TL2
IH1
IL1
IH2
IL2
HCFIG
ALMSCFIG
SCFIG
7
RW 0 1 0 0 0 0 0 20
A0
7
RW 0 1 0 1 0 0 0 28
A8
8
RW 0 1 0 0 0 1 0 22
A2
8
RW 0 1 0 1 0 1 0 2A
AA
9
RW 0 1 0 0 1 0 0 24
A4
9
RW 0 1 0 0 1 1 0 26
A6
10
RW 0 1 0 1 1 0 0 2C
AC
10 RW 0 1 0 1 1 1 0 2E
AE
11 RW 0 1 1 0 0 0 0 30
B0
12 RW 0 1 1 0 0 1 0 32
B2
13 RW 0 1 1 0 1 0 0 34
B4
ALMHCFIG
14 RW 0 1 1 0 1 1 0 36
B6
VSET1
15 RW 0 1 1 1 0 0 0 38
B8
VSET2
15
RW 0 1 1 1 1 0 0 3C
BC
HIST_APC1
16 RW 0 1 1 1 0 1 0 3A
BA
HIST_APC2
16 RW 0 1 1 1 0 1 0 3E
BE
IDAC1
17
0 1 0 1 1 0 0 0 58
—
IDAC2
17
0 1 0 1 1 1 0 0 5C
—
IODAC1
18
0 1 0 1 1 0 1 0 5A
—
IODAC2
18
0 1 0 1 1 1 1 0 5E
—
PGACAL
19
0 1 1 0 0 0 0 0 60
—
ADCCON
20
0 1 1 0 0 0 1 0 62
—
SSHUT
21
0 1 1 0 0 1 0 0 64
—
LDAC
22
0 1 1 0 0 1 1 0 66
—
—
23
0 1 1 0 1 1 1 0 6E
—
—
24 RW 1 1 1 0 0 1 0 72
80
SCLR
25
0 1 1 1 0 1 0 0 74
—
—
27
0 1 1 1 1 1 1 0 7E
—
—
26
11110110 —
F6
The following properties of the register address map should be noted:
• All register data is volatile.
• Data stored in locations TH1, TH2, TL1, TL2, IH1, IH2, IL1, IL2, HCFIG, ALMSCFIG, SCFIG, ALMHCFIG, VSET1,
VSET2, IDAC1, IDAC2, IODAC1, IODAC2, PGACAL, ADCCON, SSHUT, and LDAC can be loaded from EEPROM
at power-up or after a full reset.
• Write to the FIFO register only in LUT streaming mode (see the LUT Streaming Mode section).
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