MAX11008 Datasheet, PDF (30/67 Pages) Maxim Integrated Products – Dual RF LDMOS Bias Controller with Nonvolatile Memory

Dual RF LDMOS Bias Controller with
Nonvolatile Memory
High-Side Current-Sense
Amplifiers and PGAs
The MAX11008 provides dual high-side current-sense
and differential amplifier capability. The current-sense
amplifiers provide a 5V to 32V input common-mode
range. Both CS_+ and CS_- must be within the speci-
fied common-mode range for proper operation of each
amplifier.
The sense amplifiers measure the load current, I_LOAD,
through an external sense resistor, R_SENSE, between
the CS_+ and CS_- inputs. The full-scale sense voltage
range (V_SENSE = V_{CS_+} - V_{CS_-}) depends on the pro-
grammed gain (see the Electrical Characteristics sec-
tion). The sense amplifiers provide a voltage output at
PGAOUT1 and/or PGAOUT2, where the output voltage
is determined by the following equation:
V_{PGAOUT_} = A_PGA x (V_{CS_+} - V_{CS_-})
where A_PGA is the selected gain setting of the PGA (2,
10, or 25).
The PGA outputs are routed to the internal 12-bit ADC to
internally monitor and/or read through the serial interface.
The PGA scales the sensed voltages to fit the input range
for the ADC. Program the PGA with gains of 2, 10, and 25
by setting the PG_SET_ bits in the Hardware
Configuration register (see Tables 11 and 11c).
To increase the accuracy of drain current measure-
ments, the MAX11008 features a PGA output offset volt-
age calibration function. The PGA calibration function
has two modes of operation: acquisition mode and
tracking mode. In acquisition mode, the calibration rou-
tine operates continuously until the offset error of the
PGA is minimized. In tracking mode, the calibration
routine operates intermittently and has higher noise
thresholds (more averaging). Typically, the first calibra-
tion is performed in acquisition mode and all subse-
quent calibrations are performed in tracking mode. The
PGA Calibration Control register selects the PGA cali-
bration mode and controls when calibrations occur
(see the PGA Calibration Control Register (PGACAL)
(Write Only) section).
Since PGA calibration affects the accuracy of ADC
conversion results, avoid performing PGA calibrations
when ADC conversions are in progress. Wait at least
2µs (t_DPUEXT) after DAC power-up before performing a
PGA calibration.
First-In-First-Out (FIFO)
The MAX11008 utilizes a bidirectional FIFO that can
store up to eight 16-bit data words. The data stored in
the FIFO may consist of ADC conversion results (see
the ADC Monitoring Mode section), user data that is to
be written to the EEPROM (see the LUT Streaming
Mode section), or data that is to be read from the
EEPROM (see the Message Mode section). The data
remains in the FIFO until it can be read by the master
device through the serial data line (see the ADC
Monitoring Mode or Message Mode section) or written
to the EEPROM (see the LUT Streaming Mode section).
The proceeding sections describe the various modes
of operation and data flow control that involve the FIFO.
ADC Monitoring Mode
Setting the ADCMON (D10) bit in the Hardware
Configuration register (see Table 11) places the
MAX11008 into ADC monitoring mode. The 12-bit ADC
conversion result of the selected channel is placed into
the FIFO along with a 4-bit channel tag. The 4-bit chan-
nel tag is primarily used to indicate the origin of the
conversion, and can also be used to indicate that the
conversion data may be corrupted during FIFO over-
flow or that the FIFO is currently empty (see Tables 24
and 24a).
When multiple conversions are made, the FIFO may
overflow if data is placed into the FIFO faster than it is
read out. In this case, the FIFO stores the seven most
recent ADC conversions. When the 8th conversion
result enters the FIFO, the oldest conversion is discard-
ed, thereby leaving the seven most recent results. The
FIFOOVER bit (D8) in the Flag register (see Table 26) is
set to 1 when FIFO overflow occurs.
If the FIFO is full and overflowing on each ADC conver-
sion, there is a narrow timing window in which reading
the FIFO produces invalid data. The MAX11008 detects
this hazard and flags the data as unreliable by using
the channel tag error (1110). Only the data being read
through the serial interface is invalid. The ADC sample
used internally for V_{GATE_} calculations is valid. To avoid
overflow, systematically remove data from the FIFO.
If the ADC data is read out of the FIFO faster than data
is transferred into the FIFO, essentially emptying the
FIFO, a data word containing the empty FIFO tag
(1111) and the current status of the Flag register is
read from the FIFO.
LUT Streaming Mode
The LUT streaming mode is used to write data to the
EEPROM. Place the MAX11008 in LUT streaming mode
by writing to the LUT Streaming register (see Table 27)
and disabling the internal watchdog oscillator in the
Software Shutdown register. The FIFO is cleared when
entering LUT streaming mode, so important data
remaining in the FIFO should be read before entering
this mode. Write the data that is to be transferred to the
EEPROM to the FIFO. The MAX11008 automatically
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