LTC3811_15 Datasheet, PDF (40/48 Pages) Linear Technology – High Speed Dual, Multiphase Step-Down DC/DC Controller

LTC3811
APPLICATIONS INFORMATION
frequency switching nodes in the circuit and should
ideally be shielded (both laterally and vertically) by
ground planes.
10. If the differential remote sense amplifier is being used,
the PCB traces connecting DIFF/IN⁺ and DIFF/IN^– to
the output capacitor should avoid any high frequency
switching nodes in the circuit and should ideally be
shielded (both laterally and vertically) by ground
planes. In addition, the DIFF/IN⁺ and DIFF/IN^– PCB
traces should be routed parallel to one another with
minimum spacing in between. Due to the 160kΩ
input impedance of these pins, it is critical that these
traces avoid any high frequency switching nodes in
the circuit.
11. The high di/dt loops formed by the input capacitor
and the power MOSFETs should be kept as small as
possible to avoid EMI and differential mode switching
noise. The upper power MOSFETs should be located
close to one another and as close as possible to the
positive terminal of the input decoupling capacitor. Do
not attempt to split the input decoupling for the two
channels as it can cause a large resonant loop.
12. The bottom MOSFETs sources should also be located
close to one another and as close as possible to the
negative terminal of the input capacitor. Since the
inductor can be modeled as a current source, its
placement on the board is less critical than the high
di/dt components.
13. The switch node area should be kept small, with
the upper power MOSFET sources and lower power
MOSFET drains in close proximity.
14. The filter capacitor between the SENSE⁺ and SENSE^–
pins, as well as the filter resistors, should be located
as close as possible to the IC. In addition, the connec-
tions between the SENSE⁺ and SENSE^– filter resistors
and the sense resistor should be routed parallel to one
another with minimum spacing in between. These
traces should avoid any high frequency switching
nodes in the circuit.
15. Keep the switch nodes (SW1, SW2), the top gate
nodes (TG1, TG2) and the boost nodes (BOOST1,
BOOST2) away from sensitive small-signal nodes,
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especially from the opposite channel’s voltage- and
current-sensing feedback signals. The SW, TG and
BOOST nodes can have slew rates in excess of 1V/ns
relative to ground and should therefore be kept on
the “output side” of the LTC3811.
16. Check the stress on the power MOSFETs by indepen-
dently measuring the drain-to-source voltages directly
across the devices terminals. Beware of inductive
ringing that could exceed the maximum voltage rating
of the MOSFET. If this ringing cannot be avoided and
exceeds the maximum rating of the device, choose a
higher voltage rated MOSFET.
17. When synchronizing the LTC3811 to an external clock,
use a low impedance source such as a logic gate to
drive the MODE/SYNC pin and keep the lead as short
as possible.
18. Minimize the capacitive load on the CLKOUT pin to
minimize excess phase shift. Buffer the CLKOUT signal
with an emitter follower if necessary.
The diagram in Figure 28 illustrates all the branch currents in
a 2-phase single output switching regulator. After studying
the waveforms it is clear why it is critical to reduce the area
of the high dV/dt nodes as much as possible. High electric
and magnetic fields will radiate from these “loops,” just as
a radio station broadcasts a signal. The output capacitor
ground should return to the negative terminal of the input
capacitor and not share a common ground path with any
switched current paths. The left half of the circuit gives
rise to the “noise” generated by the switching regulator.
The ground terminations of the synchronous MOSFETs and
Schottky optional diodes should return to the bottom plate
of the input capacitor with a short, isolated PC trace since
very high di/dt currents are present. A separate, isolated
path from the negative terminals of the input and output
capacitors should be used to connect the IC signal ground
pin (SGND). This technique keeps inherent signals gener-
ated by the high di/dt current pulses from taking alternate
current paths that have finite impedances during the total
period of the switching regulator.
3811f