LTC3811_15 Datasheet, PDF (15/48 Pages) Linear Technology – High Speed Dual, Multiphase Step-Down DC/DC Controller

LTC3811
OPERATION (Refer to the Functional Diagram)
Main Control Loop
The LTC3811 uses a constant frequency peak current
mode control architecture. During normal operation, the
top MOSFET is turned on each cycle when the oscillator
sets the PWM latch and turned off when the main current
comparator (ICMP) resets the latch. The peak current at
which comparator ICMP resets the latch is controlled by
the voltage on the COMP pin, which is the output of the
error amplifier. The remote sense amplifier (DIFFAMP)
produces a signal equal to the differential voltage sensed
across the output capacitor and re-references it to the
local IC ground reference (SGND). The FB pin receives
a portion of this voltage feedback signal and compares
it to the internal 0.6V reference. When the load current
increases it causes a slight decrease in the FB pin voltage
relative to the 0.6V reference, which in turn causes the
COMP pin voltage to rise until the average inductor current
is equal to the load current.
The top MOSFET drivers are biased from a floating boot-
strap capacitor, C_B, which is normally recharged during
the off-time through an external Schottky diode. When V_IN
decreases to a voltage close to V_OUT, however, the loop
may enter dropout and attempt to turn on the top MOSFET
continuously. A dropout detector senses this condition and
forces the top MOSFET to turn off every 10th cycle for one
third of a cycle to recharge the bootstrap capacitor.
Differences Between the QFN and G36 Package
Options
The LTC3811 is offered in two package options, a 38-pin
QFN and a 36-pin SSOP. The full featured QFN package
option has no leads and an exposed lead frame that needs
to be soldered to the PCB, whereas the 36-pin SSOP has
leads and is therefore slightly easier to solder to a PCB
and to debug in the lab.
The primary electrical difference between the QFN and
SSOP options is the SSOP version lacks the CSOUT
and PHASEMODE pins. With no CSOUT pin, the SSOP
version has no provision for output voltage positioning.
With no PHASEMODE input (it is internally connected
to SGND), the SSOP version is limited to 2-phase and
4-phase applications.
In addition to differences in pinout, another difference
between the two package options is their thermal resis-
tance. The QFN package, by virtue of its exposed lead
frame, has a junction-to-ambient thermal resistance of
only 34°C/W, whereas the SSOP package has a thermal
resistance of 100°C/W. The power dissipation of the IC
is a function of the input voltage, the gate charge of the
external power MOSFETs and the operating frequency.
The gate charge losses can be partially mitigated by us-
ing the EXTV_CC input to supply power to the IC, but users
should beware that high input voltage applications using
very high gate charge power MOSFETs, that also need to
operate at high frequency, should only be attempted using
the QFN package option. More details covering thermal
management are given later in this data sheet.
Supplying Power to the LTC3811
The LTC3811 features several power supply input pins
and multiple ways of supplying power to the gate drivers
and low voltage analog control circuitry.
The first method of supplying power to the IC uses the
internal low dropout linear regulator (LDO) that draws
power from V_IN and regulates DRV_CC to 6V, as shown in
Figure 1. The DRV_CC input supplies power to the internal
gate drivers, which are capable of very high peak transient
charge (1A) and discharge (5A) currents. The DRV_CC supply
should be decoupled to PGND with a minimum of 4.7μF
low ESR ceramic (X5R or better) capacitance. If multiple
power MOSFETs are being driven in parallel for high cur-
rent applications it is recommended that this capacitance
V_IN
V_IN
EXTV_CC
4.5V +
–
6V
LDO
DRV_CC
INTV_CC
SGND
BIAS
GATE DRIVER SUPPLY
ANALOG SUPPLY
–
V_FB
SS/TRACK ₊EA
0.600V
3811 F01
Figure 1. Supplying Power to the LTC3811 from V_IN
3811f
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