LTC3811_15 Datasheet, PDF (33/48 Pages) Linear Technology – High Speed Dual, Multiphase Step-Down DC/DC Controller

LTC3811
APPLICATIONS INFORMATION
to MODE/SYNC, is shown in Figure 21 and specified in the
Electrical Characteristics table. Note that the LTC3811 can
only be synchronized to an external clock whose frequency
is within range of the LTC3811’s internal VCO, which is
nominally 125kHz to 1.1MHz. This is guaranteed to be
between 175kHz and 900kHz. A simplified block diagram
is shown in Figure 22.
If the external clock frequency is greater than the internal
oscillator’s frequency, f_OSC, then current is sourced con-
tinuously from the phase detector output, pulling up the
PLL/LPF pin. When the external clock frequency is less
than f_OSC, current is sunk continuously, pulling down
the PLL/LPF pin. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. The voltage on the PLL/LPF pin is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
the filter capacitor C_LP holds the voltage.
The loop filter components, C_LP and R_LP, smooth out
the current pulses from the phase detector and provide a
stable input to the voltage-controlled oscillator. The filter
components C_LP and R_LP determine how fast the loop
acquires lock. Typically R_LP = 10k and C_LP is 2200pF
to 0.01μF.
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
0
0.5
1
1.5
2
PLL/LPF PIN VOLTAGE (V)
2.5
3811 G36
Figure 21. Relationship Between Oscillator Frequency
and Voltage at the PLL/LPF Pin When Synchronizing to
an External Clock
EXTERNAL
OSCILLATOR
MODE/
SYNC
DIGITAL
PHASE/
FREQUENCY
DETECTOR
2.4V
R_LP
C_LP
PLL/LPF
OSCILLATOR
3811 F22
Figure 22. Phase-Locked Loop Block Diagram
Typically, the external clock (on MODE/SYNC pin) input
high threshold is 1.1V, while the input low threshold
is 1.0V.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3811 circuits: 1) IC V_IN current, 2) DRV_CC
regulator current, 3) I²R losses, 4) Topside MOSFET
transition losses.
1. The V_IN current has two components: the first is the
DC supply current given in the Electrical Characteristics
table, and the second is the MOSFET driver and control
currents.
2. DRV_CC current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched
from low to high to low again, a packet of charge dQ
3811f
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