LTC3811_15 Datasheet, PDF (30/48 Pages) Linear Technology – High Speed Dual, Multiphase Step-Down DC/DC Controller

LTC3811
APPLICATIONS INFORMATION
C_IN and C_OUT Selection
In continuous mode, the drain current of each top N-channel
MOSFET is a square wave of duty cycle V_OUT/V_IN. A low ESR
input capacitor sized for the maximum RMS current must
be used. The details of a close form equation can be found
in Application Note 77. Figure 17 shows the input capacitor
ripple current for different phase configurations with the
output voltage fixed and input voltage varied. The input
ripple current is normalized against the DC output current.
The graph can be used in place of tedious calculations. The
minimum input ripple current can be achieved when the
product of phase number and output voltage, N(V_OUT), is
approximately equal to the input voltage V_IN or:
V_OUT
V_IN
=
k
N
where
k=
1,
2,
...,
N–
1
So the phase number can be chosen to minimize the input
capacitor size for the given input and output voltages.
In the graph of Figure 17, the local maximum input RMS
capacitor currents are reached when:
V_OUT
V_IN
=
2k − 1
2N
where
k
=
1,
2,
...,
N
These worst-case conditions are commonly used for design
because even significant deviations do not offer much relief.
Note that capacitor manufacturer’s ripple current ratings
are often based on only 2000 hours of life. This makes
it advisable to further derate the capacitor, or to choose
a capacitor rated at a higher temperature than required.
Several capacitors may also be paralleled to meet size or
height requirements in the design. Always consult the
capacitor manufacturer if there is any question.
The graph shows that the peak RMS input current is
reduced linearly, inversely proportional to the number, N
of stages used. It is important to note that the efficiency
loss is proportional to the input RMS current squared and
therefore a 2-stage implementation results in 75% less
power loss when compared to a single phase design. Bat-
tery/input protection fuse resistance (if used), PC board
trace and connector resistance losses are also reduced
by the reduction of the input ripple current in a PolyPhase
0.6
0.5
1-PHASE
0.4
2-PHASE
3-PHASE
0.3
4-PHASE
6-PHASE
0.2
0.1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
DUTY FACTOR (V_OUT/V_IN)
3811 F17
Figure 17. Normilized Input RMS Ripple Current vs
Duty Factor for 1 to 6 Output Stages
system. The required amount of input capacitance is further
reduced by the factor, N, due to the effective increase in
the frequency of the current pulses.
The selection of C_OUT is driven by the required effective
series resistance (ESR). Typically once the ESR require-
ment has been met, the RMS current rating generally far
exceeds the I_RIPPLE(P-P) requirements. The steady-state
output ripple (ΔV_OUT) is determined by:
ΔV_OUT
≈
ΔI_RIPPLE
⎡⎢_{ESR +}
⎣
1
8NfC_OUT
⎤
⎥
⎦
where f = operating frequency of each stage, N is the
number of phases, C_OUT = output capacitance and
ΔI_RIPPLE = combined inductor ripple currents.
The output ripple varies with input voltage since ΔI_L is a
function of input voltage. The output ripple will be less than
50mV at max V_IN with ΔI_L = 0.4I_OUT(MAX)/N assuming:
C_OUT required ESR < 2N(R_SENSE) and
C_OUT > 1/(8Nf)(R_SENSE)
The emergence of very low ESR ceramic capacitors in
small, surface mount packages makes very physically
small implementations possible. The ability to externally
compensate the switching regulator loop using the
LTC3811’s true operational error amplifier allows a much
wider selection of output capacitor types. The ability to
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