LTC3811_15 Datasheet, PDF (39/48 Pages) Linear Technology – High Speed Dual, Multiphase Step-Down DC/DC Controller

LTC3811
APPLICATIONS INFORMATION
the maximum load current that represents the minimum
RMS current rating of the input capacitor. The worst-case
condition occurs when only one output is operational. The
output with the highest (V_OUT)(I_OUT) product should be
used to determine the minimum RMS current rating of the
input capacitor. From Figure 17 we can see that the worst
case condition for this output occurs at the maximum duty
cycle of 33.3%, and that the minimum RMS current rating
of the input capacitor needs to exceed 7A (47% of 15A).
The ceramic output capacitors chosen have an effective
ESR of 5mΩ and a bulk capacitance of 660μF. The peak-
to-peak output ripple for this configuration is:
ΔV_OUT
=
ΔI_L
•
⎡⎢_ESR
⎣
+
8
•
n
•
1
f•
C_OUT
⎤
⎥
⎦
=
6.7A
•
⎡⎣⎢_0.005Ω
+
8
•
2
•
1
500kHz
•
660μF
⎤
⎦⎥
ΔV_OUT = 33.5mV + 1.3mV = 34.8mV
This represents a ripple voltage of 2.3%. As can be seen
from the calculation, the biggest portion of the output ripple
comes from the ESR of the capacitor. This is why low ESR
ceramic capacitors are so important in low voltage, high
current applications.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the converter:
1. The connection between the SGND pin on the LTC3811
and all of the small-signal components surrounding
the IC should be isolated from the power ground and
PGND pin, and should be Kelvin-connected to the main
ground node near the bottom terminal of the output
capacitors.
2. Place the small-signal components away from high
frequency switching nodes on the board. The pinout of
the LTC3811 was carefully designed in order to make
component placement as easy and noise free as pos-
sible. All of the power components can be placed on
one side of the IC, away from all of the small-signal
components.
3. The bottom terminals of the input and output capacitors
should be placed as close as possible to one another,
with the small-signal ground connection in between
them. This component arrangement will reduce dif-
ferential mode noise due to the two high di/dt loops
in the power circuit.
4. If the output capacitor is located far away from the
IC and the remote sense differential amplifier is being
used to level-shift the output voltage back to the local
IC ground, the small-signal ground around the LTC3811
should be Kelvin-connected to the main ground node
near the bottom terminal of the input capacitor.
5. The PGND pin should be connected to the sources
of the bottom MOSFETs using a wide, short trace on
the top layer of the board. The MOSFETs should also
be placed on the top layer of the board. The exposed
area on the bottom of the QFN package is internally
connected to the PGND node of the IC.
6. Place the INTV_CC analog supply decoupling capacitor
and resistor right next to the INTV_CC and SGND pins
on the same layer as the IC. A low ESR 0.1μF to 1μF
ceramic capacitor should be used.
7. Place the DRV_CC gate driver supply decoupling capaci-
tor right next the DRV_CC and PGND pins, on the same
layer as the IC. This capacitor carries high di/dt MOSFET
gate drive currents. A low ESR (X5R or better) 4.7μF
to 10μF ceramic capacitor should be used.
8. The floating gate driver supply decoupling capacitor
should be located right next the BOOST and SW pins,
on the same layer as the IC. This capacitor carries high
di/dt currents to drive the upper power MOSFETs. A
low ESR (X5R or better) ceramic capacitor at least 100
times the total input capacitance of the upper power
MOSFETs for that channel should be used.
9. The resistor divider connected to the FB pin to program
the output voltage should be located as near as pos-
sible to the IC, with the bottom resistor connecting to
the isolated signal ground node near the SGND pin.
The PCB trace connecting the top resistor to the upper
terminal of the output capacitor should avoid any high
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